Due to asynchronicity between the main clock domain and the peripheral clock domain, the Control A (WDT.CTRLA) register is synchronized when written. The Synchronization Busy (SYNCBUSY) flag in the STATUS (WDT.STATUS) register indicates if there is an ongoing synchronization.

Writing to WDT.CTRLA while SYNCBUSY=1 is not allowed.

The following registers are synchronized when written:

The WDR instruction will need two to three cycles of the WDT clock to be synchronized. Issuing a new WDR instruction while a WDR instruction is being synchronized will be ignored.