MUXCTRLA

MUX Control A

ACn.MUXCTRLA controls the analog comparator MUXes.

Name:: MUXCTRLA
Offset:: 0x02
Reset:: 0x00
Access:: -

Bit7	6	5	4	3	2	1	0
INVERT			MUXPOS[1:0]			MUXNEG[1:0]
AccessR/W			R/W	R/W		R/W	R/W
Reset0			0	0		0	0

Bit 7 – INVERT: Invert AC Output

Invert AC Output

Writing a ‘1’ to this bit enables inversion of the output of the AC. This effectively inverts the input to all the peripherals connected to the signal and affects the internal status signals.

Bits 4:3 – MUXPOS[1:0]: Positive Input MUX Selection

Positive Input MUX Selection

Writing to this bit field selects the input signal to the positive input of the AC.

Value	Name	Description
`0x0`	AINP0	Positive pin 0
`0x0`	AINP1⁽¹⁾	Positive pin 1
`Other`	-	Reserved

Note:

1.Not all pins of a port are available on devices with low pin counts. Check the Pinout Diagram and/or the I/O Multiplexing table for details.

Bits 1:0 – MUXNEG[1:0]: Negative Input MUX Selection

Negative Input MUX Selection

Writing to this bit field selects the input signal to the negative input of the AC.

Value	Name	Description
`0x0`	AINN0	Negative pin 0
`0x1`	AINN1⁽¹⁾	Negative pin 1
`0x2`	VREF	Voltage Reference
`0x3`	DAC	DAC output

Note:

1.Not all pins of a port are available on devices with low pin counts. Check the Pinout Diagram and/or the I/O Multiplexing table for details.