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28/40/44/48-Pin, Low-Power, High-Performance Microcontroller with XLP Technology
Introduction
PIC18-Q83 Family Types
Features
Memory
Operating Characteristics
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
1 Packages
2 Pin Diagrams
3 Pin Allocation Tables
4 Guidelines for Getting Started with PIC18-Q83 Microcontrollers
4.1 Basic Connection Requirements
4.2 Power Supply Pins
4.3 Master Clear (MCLR) Pin
4.4 In-Circuit Serial Programming™ (ICSP™) Pins
4.5 External Oscillator Pins
4.6 Unused I/Os
5 Register and Bit Naming Conventions
5.1 Register Names
5.2 Bit Names
5.3 Register and Bit Naming Exceptions
6 Register Legend
7 PIC18 CPU
7.1 System Arbitration
7.2 Memory Access Scheme
7.3 8x8 Hardware Multiplier
7.4 PIC18 Instruction Cycle
7.5 STATUS Register
7.6 Call Shadow Register
7.7 Register Definitions: System Arbiter
7.8 Register Summary - System Arbiter Control
8 Device Configuration
8.1 Configuration Settings
8.2 Code Protection
8.3 User ID
8.4 Device ID and Revision ID
8.5 Register Definitions: Configuration Words
8.6 Register Summary - Configuration Settings
8.7 Register Definitions: Device ID and Revision ID
8.8 Register Summary - DEVID/REVID
9 Memory Organization
9.1 Program Memory Organization
9.2 Device Information Area
9.3 Device Configuration Information
9.4 Data Memory Organization
9.5 Data Addressing Modes
9.6 Data Memory and the Extended Instruction Set
9.7 Register Definitions: Memory Organization
9.8 Register Summary - Memory Organization
10 NVM - Nonvolatile Memory Module
10.1 Operations
10.2 Unlock Sequence
10.3 Program Flash Memory (PFM)
10.4 Data Flash Memory (DFM)
10.5 Register Definitions: NVM
10.6 Register Summary - NVM
11 VIC - Vectored Interrupt Controller Module
11.1 Overview
11.2 Interrupt Control and Status Registers
11.3 Interrupt Vector Table
11.4 Interrupt Priority
11.5 Interrupt Operation
11.6 Context Saving
11.7 Returning from Interrupt Service Routine (ISR)
11.8 Interrupt Latency
11.9 Interrupt Setup Procedure
11.10 External Interrupt Pins
11.11 Wake-Up from Sleep
11.12 Interrupt Compatibility
11.13 Register Definitions: Interrupt Control
11.14 Register Summary - Interrupts
12 OSC - Oscillator Module (With Fail-Safe Clock Monitor)
12.1 Clock Source Types
12.2 Clock Switching
12.3 Fail-Safe Clock Monitor (FSCM)
12.4 Active Clock Tuning (ACT)
12.5 Register Definitions: Oscillator Module
12.6 Register Summary - Oscillator Module
13 CRC - Cyclic Redundancy Check Module with Memory Scanner
13.1 Module Overview
13.2 Polynomial Implementation
13.3 Data Sources
13.4 CRC Check Value
13.5 CRC Interrupt
13.6 Configuring the CRC Module
13.7 Scanner Module Overview
13.8 Scanning Modes
13.9 Configuring the Scanner
13.10 Scanner Interrupt
13.11 Peripheral Module Disable
13.12 CRC-on-Boot Module Overview
13.13 Register Definitions: CRC and Scanner Control
13.14 Register Summary - CRC
14 Resets
14.1 Power-on Reset (POR)
14.2 Brown-out Reset (BOR)
14.3 Low-Power Brown-out Reset (LPBOR)
14.4 MCLR Reset
14.5 Windowed Watchdog Timer (WWDT) Reset
14.6 RESET Instruction
14.7 Stack Overflow/Underflow Reset
14.8 Programming Mode Exit
14.9 Power-up Timer (PWRT)
14.10 Start-Up Sequence
14.11 Determining the Cause of a Reset
14.12 Power Control (PCON0/PCON1) Registers
14.13 Register Definitions: Power Control
14.14 Register Summary - BOR Control and Power Control
15 WWDT - Windowed Watchdog Timer
15.1 Independent Clock Source
15.2 WWDT Operating Modes
15.3 Time-Out Period
15.4 Watchdog Window
15.5 Clearing the Watchdog Timer
15.6 Operation During Sleep
15.7 Register Definitions: Windowed Watchdog Timer Control
15.8 Register Summary - WDT Control
16 DMA - Direct Memory Access
16.1 DMA Registers
16.2 DMA Organization
16.3 DMA Interface
16.4 Disable DMA Message Transfer Upon Completion
16.5 Types of Hardware Triggers
16.6 Types of Data Transfers
16.7 DMA Interrupts
16.8 DMA Setup and Operation
16.9 Reset
16.10 Power-Saving Mode Operation
16.11 Example Setup Code
16.12 Register Overlay
16.13 Register Definitions: DMA
16.14 Register Summary - DMA
17 Power-Saving Modes
17.1 Doze Mode
17.2 Sleep Mode
17.3 Idle Mode
17.4 Peripheral Operation in Power-Saving Modes
17.5 Register Definitions: Power-Savings Control
17.6 Register Summary - Power-Savings Control
18 PMD - Peripheral Module Disable
18.1 Overview
18.2 Disabling a Module
18.3 Enabling a Module
18.4 Register Definitions: Peripheral Module Disable
18.5 Register Summary - PMD
19 I/O Ports
19.1 Overview
19.2 PORTx - Data Register
19.3 LATx - Output Latch
19.4 TRISx - Direction Control
19.5 ANSELx - Analog Control
19.6 WPUx - Weak Pull-Up Control
19.7 INLVLx - Input Threshold Control
19.8 SLRCONx - Slew Rate Control
19.9 ODCONx - Open-Drain Control
19.10 Edge Selectable Interrupt-on-Change
19.11 I2C Pad Control
19.12 I/O Priorities
19.13 MCLR/VPP/RE3 Pin
19.14 Register Definitions: Port Control
19.15 Register Summary - I/O Ports
20 IOC - Interrupt-on-Change
20.1 Overview
20.2 Enabling the Module
20.3 Individual Pin Configuration
20.4 Interrupt Flags
20.5 Clearing Interrupt Flags
20.6 Operation in Sleep
20.7 Register Definitions: Interrupt-on-Change Control
20.8 Register Summary - Interrupt-on-Change Control
21 PPS - Peripheral Pin Select Module
21.1 Overview
21.2 PPS Inputs
21.3 PPS Outputs
21.4 Bidirectional Pins
21.5 PPS Lock
21.6 Operation During Sleep
21.7 Effects of a Reset
21.8 Register Definitions: Peripheral Pin Select (PPS)
21.9 Register Summary - Peripheral Pin Select Module
22 CLC - Configurable Logic Cell
22.1 CLC Setup
22.2 CLC Interrupts
22.3 Effects of a Reset
22.4 Output Mirror Copies
22.5 Operation During Sleep
22.6 CLC Setup Steps
22.7 Register Overlay
22.8 Register Definitions: Configurable Logic Cell
22.9 Register Summary - CLC Control
23 CLKREF - Reference Clock Output Module
23.1 Clock Source
23.2 Programmable Clock Divider
23.3 Selectable Duty Cycle
23.4 Operation in Sleep Mode
23.5 Register Definitions: Reference Clock
23.6 Register Summary - Reference CLK
24 TMR0 - Timer0 Module
24.1 Timer0 Operation
24.2 Clock Selection
24.3 Timer0 Output and Interrupt
24.4 Operation During Sleep
24.5 Register Definitions: Timer0 Control
24.6 Register Summary - Timer0
25 TMR1 - Timer1 Module with Gate Control
25.1 Timer1 Operation
25.2 Clock Source Selection
25.3 Timer1 Prescaler
25.4 Secondary Oscillator
25.5 Timer1 Operation in Asynchronous Counter Mode
25.6 Timer1 16-Bit Read/Write Mode
25.7 Timer1 Gate
25.8 Timer1 Interrupt
25.9 Timer1 Operation During Sleep
25.10 CCP Capture/Compare Time Base
25.11 CCP Special Event Trigger
25.12 Peripheral Module Disable
25.13 Register Definitions: Timer1 Control
25.14 Register Summary - Timer1
26 TMR2 - Timer2 Module
26.1 Timer2 Operation
26.2 Timer2 Output
26.3 External Reset Sources
26.4 Timer2 Interrupt
26.5 PSYNC Bit
26.6 CSYNC Bit
26.7 Operating Modes
26.8 Operation Examples
26.9 Timer2 Operation During Sleep
26.10 Register Definitions: Timer2 Control
26.11 Register Summary - Timer2
27 SMT - Signal Measurement Timer
27.1 SMT Operation
27.2 Register Definitions: SMT Control
27.3 Register Summary - SMT Control
28 UTMR - Universal Timer Module
28.1 Module Nomenclature
28.2 Clock Source Selection
28.3 UTMR Prescaler
28.4 UTMR Operation
28.5 UTMR Output Modes
28.6 Interrupt and DMA Triggers
28.7 Operation During Sleep
28.8 Chaining Counter Timers
28.9 Register Definitions: Universal Timer
28.10 Register Summary - Universal Timer
29 CCP - Capture/Compare/PWM Module
29.1 CCP Module Configuration
29.2 Capture Mode
29.3 Compare Mode
29.4 PWM Overview
29.5 Register Definitions: CCP Control
29.6 Register Summary - CCP Control
30 Capture, Compare, and PWM Timers Selection
30.1 Register Definitions: Capture, Compare, and PWM Timers Selection
30.2 Register Summary - Capture, Compare, and PWM Timers Selection
31 PWM - Pulse-Width Modulator with Compare
31.1 Output Slices
31.2 Period Timer
31.3 Clock Sources
31.4 External Period Resets
31.5 Buffered Period and Parameter Registers
31.6 Synchronizing Multiple PWMs
31.7 Interrupts
31.8 Operation During Sleep
31.9 Register Definitions: PWM Control
31.10 Register Summary - PWM
32 CWG - Complementary Waveform Generator Module
32.1 Fundamental Operation
32.2 Operating Modes
32.3 Clock Source
32.4 Selectable Input Sources
32.5 Output Control
32.6 Dead-Band Control
32.7 Rising Edge and Reverse Dead Band
32.8 Falling Edge and Forward Dead Band
32.9 Dead-Band Jitter
32.10 Auto-Shutdown
32.11 Auto-Shutdown Restart
32.12 Operation During Sleep
32.13 Configuring the CWG
32.14 Register Definitions: CWG Control
32.15 Register Summary - CWG
33 NCO - Numerically Controlled Oscillator Module
33.1 NCO Operation
33.2 Fixed Duty Cycle Mode
33.3 Pulse Frequency Mode
33.4 Output Polarity Control
33.5 Interrupts
33.6 Effects of a Reset
33.7 Operation in Sleep
33.8 Register Definitions: NCO
33.9 Register Summary - NCO
34 DSM - Data Signal Modulator Module
34.1 DSM Operation
34.2 Carrier Synchronization
34.3 Carrier Source Polarity Select
34.4 Programmable Modulator Data
34.5 Modulated Output Polarity
34.6 Operation in Sleep Mode
34.7 Effects of a Reset
34.8 Peripheral Module Disable
34.9 Register Definitions: Modulation Control
34.10 Register Summary - DSM
35 UART - Universal Asynchronous Receiver Transmitter with Protocol Support
35.1 UART I/O Pin Configuration
35.2 UART Asynchronous Modes
35.3 DMX Mode (Full-Featured UARTs Only)
35.4 LIN Modes (Full-Featured UARTs Only)
35.5 DALI Mode (Full-Featured UARTs Only)
35.6 General Purpose Manchester (Full-Featured UARTs Only)
35.7 Polarity
35.8 Stop Bits
35.9 Operation After FIFO Overflow
35.10 Receive and Transmit Buffers
35.11 Flow Control
35.12 Checksum (Full-Featured UARTs Only)
35.13 Collision Detection (Full-Featured UARTs Only)
35.14 RX/TX Activity Time-Out
35.15 Clock Accuracy with Asynchronous Operation
35.16 UART Baud Rate Generator
35.17 Transmitting a Break
35.18 Receiving a Break
35.19 UART Operation During Sleep
35.20 Register Definitions: UART
35.21 Register Summary - UART
36 SPI - Serial Peripheral Interface Module
36.1 SPI Controls
36.2 SPI Operation
36.3 Host Mode
36.4 Client Mode
36.5 SPI Operation in Sleep Mode
36.6 SPI Interrupts
36.7 Register Definitions: Serial Peripheral Interface
36.8 Register Summary - SPI Control
37 I2C - Inter-Integrated Circuit Module
37.1 I2C Features
37.2 I2C Terminology
37.3 I2C Module Overview
37.4 I2C Operation
37.5 Register Definitions: I2C Control
37.6 Register Summary - I2C
38 CAN - Controller Area Network
38.1 Module Overview
38.2 Modes of Operation
38.3 Configuration
38.4 CAN Message Frames
38.5 Message Transmission
38.6 Transmit Event FIFO (TEF)
38.7 Message Filtering
38.8 Message Reception
38.9 FIFO Behavior
38.10 Timestamping
38.11 Interrupts
38.12 Error Handling
38.13 Register Definitions: CAN Control
38.14 Register Summary - CAN
39 JTAG Boundary Scan
39.1 Test Access Port (TAP) and TAP Controller
39.2 JTAG Registers
39.3 Boundary Scan Register (BSR)
39.4 JTAG Instructions
39.5 Boundary Scan Testing
39.6 Effects of Reset
40 HLVD - High/Low-Voltage Detect
40.1 Operation
40.2 Setup
40.3 Current Consumption
40.4 HLVD Start-Up Time
40.5 Applications
40.6 Operation During Sleep
40.7 Operation During Idle and Doze Modes
40.8 Effects of a Reset
40.9 Register Definitions: HLVD Control
40.10 Register Summary - HLVD
41 FVR - Fixed Voltage Reference
41.1 Independent Gain Amplifiers
41.2 FVR Stabilization Period
41.3 Register Definitions: FVR
41.4 Register Summary - FVR
42 Temperature Indicator Module
42.1 Module Operation
42.2 Temperature Calculation
42.3 ADC Acquisition Time
42.4 Register Definitions: Temperature Indicator
42.5 Register Summary - Temperature Indicator
43 ADC - Analog-to-Digital Converter with Computation and Context Module
43.1 ADC Configuration
43.2 ADC Operation
43.3 ADC Acquisition Requirements
43.4 ADC Charge Pump
43.5 Computation Operation
43.6 Channel Sequencer and Context
43.7 Register Definitions: ADC Control
43.8 Register Summary - ADC
44 DAC - Digital-to-Analog Converter Module - 8-Bit
44.1 Output Voltage Selection
44.2 Ratiometric Output Level
44.3 Operation During Sleep
44.4 Effects of a Reset
44.5 Register Definitions: DAC Control
44.6 Register Summary - DAC
45 CMP - Comparator Module
45.1 Comparator Overview
45.2 Comparator Control
45.3 Comparator Output Synchronization
45.4 Comparator Hysteresis
45.5 Comparator Interrupt
45.6 Comparator Positive Input Selection
45.7 Comparator Negative Input Selection
45.8 Comparator Response Time
45.9 Analog Input Connection Considerations
45.10 Operation in Sleep Mode
45.11 ADC Auto-Trigger Source
45.12 Register Definitions: Comparator Control
45.13 Register Summary - Comparator
46 ZCD - Zero-Cross Detection Module
46.1 External Resistor Selection
46.2 ZCD Logic Output
46.3 ZCD Logic Polarity
46.4 ZCD Interrupts
46.5 Correction for ZCPINV Offset
46.6 Handling VPEAK Variations
46.7 Operation During Sleep
46.8 Effects of a Reset
46.9 Disabling the ZCD Module
46.10 Register Definitions: ZCD Control
46.11 Register Summary - ZCD
47 Instruction Set Summary
47.1 Standard Instruction Set
47.2 Extended Instruction Set
48 ICSP™ - In-Circuit Serial Programming™
48.1 High-Voltage Programming Entry Mode
48.2 Low-Voltage Programming Entry Mode
48.3 Common Programming Interfaces
49 Register Summary
50 Electrical Specifications
50.1 Absolute Maximum Ratings(†)
50.2 Standard Operating Conditions
50.3 DC Characteristics
50.4 AC Characteristics
51 DC and AC Characteristics Graphs and Tables
51.1 Analog-to-Digital Converter (12-bit) Graphs
51.2 Brown-Out Reset Graphs
51.3 Digital-to-Analog Converter Graphs
51.4 Fixed Voltage Reference Graphs
51.5 HFINTOSC Graphs
51.6 HFINTOSC Wake From Sleep Graphs
51.7 High/Low-Voltage Detect Graphs
51.8 I/O Graphs
51.9 IDD Graphs
51.10 IPD Graphs
51.11 LFINTOSC Graphs
51.12 LFINTOSC Wake From Sleep Graphs
51.13 Low-Power Brown-Out Reset Graphs
51.14 MFINTOSC Graphs
51.15 Power-On Reset Graphs
51.16 Weak Pull-Up Graphs
52 Packaging Information
52.1 Package Details
53 Appendix A: Revision History
Microchip Information
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