16.20.41 Clock Configuration Register
Name: | HSMC_CLKCFG |
Offset: | 0x7AC |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CLKEDGE | CLKEN | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CLKDIV[8] | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CLKDIV[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 17 – CLKEDGE SMC Clock Edge
Value | Description |
---|---|
0 | The start of the external bus access is aligned with the rising edge of the SMC clock output. |
1 | The start of the external bus access is aligned with the falling edge of the SMC clock output. |
Bit 16 – CLKEN SMC Clock Enable
Value | Description |
---|---|
0 | The SMC clock is disabled. |
1 | The SMC clock is enabled. |