16.20.6 NFC Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: Disables the corresponding interrupt.

1: Enables the corresponding interrupt.

Name:	HSMC_IMR
Offset:	0x014
Reset:	0x00000000
Property:	Read-only


Bit	31	30	29	28	27	26	25	24
								RB_EDGE0
Access								R
Reset								0


Bit	23	22	21	20	19	18	17	16
	NFCASE	AWB	UNDEF	DTOE			CMDDONE	XFRDONE
Access	R	R	R	R			R	R
Reset	0	0	0	0			0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
			RB_FALL	RB_RISE
Access			R	R
Reset			0	0

Bit 24 – RB_EDGE0 Ready/Busy Line 0 Interrupt Mask

Bit 23 – NFCASE NFC Access Size Error Interrupt Mask

Bit 22 – AWB Accessing While Busy Interrupt Mask

Bit 21 – UNDEF Undefined Area Access Interrupt Mask5

Bit 20 – DTOE Data Timeout Error Interrupt Mask

Bit 17 – CMDDONE Command Done Interrupt Mask

Bit 16 – XFRDONE Transfer Done Interrupt Mask

Bit 5 – RB_FALL Ready Busy Falling Edge Detection Interrupt Mask

Bit 4 – RB_RISE Ready Busy Rising Edge Detection Interrupt Mask

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