38.6.26 ADC FIFO Mode Register
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
| Name: | ADC_FMR |
| Offset: | 0xE4 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIFOCNT[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHUNK[3:0] | ENLEVEL | ENFIFO | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 23:16 – FIFOCNT[7:0] FIFO Count
Number of conversions available in the FIFO (not a source of interrupt).
Bits 7:4 – CHUNK[3:0] Chunk Size
Number of elements in FIFO required to generate a DMA request. Allowed values are 1, 2, 4, 8.
Bit 1 – ENLEVEL Enable Level
| Value | Description |
|---|---|
| 0 |
Request to DMA is generated as soon as one data is written in FIFO when FIFO is enabled. CHUNK is not used. |
| 1 |
Request to DMA is generated as soon as the number of written elements in the FIFO is greater than or equal to CHUNK. |
Bit 0 – ENFIFO Enable FIFO
| Value | Description |
|---|---|
| 0 | FIFO is disabled. |
| 1 | FIFO is enabled. |