67.7.18 TC Block Mode Register

This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.

The External Clock Signal x Selection (TCxXCxS) bit field mentions pin names of the first Timer Counter module (TC0). For any subsequent instances, the signal numbering increments. For example, "TCLK3-TCLK5", "TIOA3-TIOA5" and "TIOB3-TIOB5" are the external I/O pins of the second Timer Counter module (TC1).

Name: TC_BMR
Offset: 0xC4
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
   MAXCMP[3:0]MAXFILT[5:4] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
 MAXFILT[3:0] AUTOCIDXPHBSWAP 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 15141312111098 
 INVIDXINVBINVAEDGPHAQDTRANSSPEEDENPOSENQDEN 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
   TC2XC2S[1:0]TC1XC1S[1:0]TC0XC0S[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 29:26 – MAXCMP[3:0] Maximum Consecutive Missing Pulses

ValueDescription
0 The flag MPE in TC_QISR never rises.
1–15 Defines the number of consecutive missing pulses before a flag report.

Bits 25:20 – MAXFILT[5:0] Maximum Filter

Pulses with a period shorter than MAXFILT+1 peripheral clock cycles are discarded. For more details on MAXFILT constraints, see Input Preprocessing.

ValueDescription
1–63 Defines the filtering capabilities.

Bit 18 – AUTOC AutoCorrection of Missing Pulses

ValueNameDescription
0 DISABLED The detection and autocorrection function is disabled.
1 ENABLED The detection and autocorrection function is enabled.

Bit 17 – IDXPHB Index Pin is PHB Pin

ValueDescription
0 IDX pin of the rotary sensor must drive TIOA1.
1 IDX pin of the rotary sensor must drive TIOB0.

Bit 16 – SWAP Swap PHA and PHB

ValueDescription
0 No swap between PHA and PHB.
1 Swap PHA and PHB internally, prior to driving the QDEC.

Bit 15 – INVIDX Inverted Index

ValueDescription
0 IDX (TIOA1) is directly driving the QDEC.
1 IDX is inverted before driving the QDEC.

Bit 14 – INVB Inverted PHB

ValueDescription
0 PHB (TIOB0) is directly driving the QDEC.
1 PHB is inverted before driving the QDEC.

Bit 13 – INVA Inverted PHA

ValueDescription
0 PHA (TIOA0) is directly driving the QDEC.
1 PHA is inverted before driving the QDEC.

Bit 12 – EDGPHA Edge on PHA Count Mode

ValueDescription
0 Edges are detected on PHA only.
1 Edges are detected on both PHA and PHB.

Bit 11 – QDTRANS Quadrature Decoding Transparent

ValueDescription
0 Full quadrature decoding logic is active (direction change detected).
1 Quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed.

Bit 10 – SPEEDEN Speed Enabled

ValueDescription
0 Disabled.
1 Enables the speed measure on channel 0, the time base being provided by channel 2.

Bit 9 – POSEN Position Enabled

ValueDescription
0 Disable position.
1 Enables the position measure on channel 0 and 1.

Bit 8 – QDEN Quadrature Decoder Enabled

Quadrature decoding (direction change) can be disabled using QDTRANS bit.

One of the POSEN or SPEEDEN bits must be also enabled.

ValueDescription
0 Disabled.
1 Enables the QDEC (filter, edge detection and quadrature decoding).

Bits 5:4 – TC2XC2S[1:0] External Clock Signal 2 (XC2) Selection

See Clock Selection for more details.
ValueNameDescription
0 TCLK2 Signal connected to XC2: TCLK2
1 Reserved
2 TIOA0 Signal connected to XC2: internal TIOA0 for chaining
3 TIOA1 Signal connected to XC2: internal TIOA1 for chaining

Bits 3:2 – TC1XC1S[1:0] External Clock Signal 1 (XC1) Selection

See Clock Selection for more details.
ValueNameDescription
0 TCLK1 Signal connected to XC1: TCLK1
1 Reserved
2 TIOA0 Signal connected to XC1: internal TIOA0 for chaining
3 TIOA2 Signal connected to XC1: internal TIOA2 for chaining

Bits 1:0 – TC0XC0S[1:0] External Clock Signal 0 (XC0) Selection

See Clock Selection for more details.
ValueNameDescription
0 TCLK0 Signal connected to XC0: TCLK0
1 Reserved
2 TIOA1 Signal connected to XC0: internal TIOA1 for chaining
3 TIOA2 Signal connected to XC0: internal TIOA2 for chaining