67.7.25 TC Write Protection Mode Register
| Name: | TC_WPMR |
| Offset: | 0xE4 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WPKEY[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPKEY[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPKEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FIRSTE | WPCREN | WPITEN | WPEN | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 31:8 – WPKEY[23:0] Write Protection Key
| Value | Name | Description |
|---|---|---|
| 0x54494D | PASSWD | Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. |
Bit 4 – FIRSTE First Error Report Enable
| Value | Description |
|---|---|
| 0 | The last write protection violation source is reported in TC_SSRx.WPVSRC and the last software control error type is reported in TC_SSRx.SWETYP. The TC_SRx.SECE flag is set at the first error occurrence within a series. |
| 1 | Only the first write protection violation source is reported in TC_SSRx.WPVSRC and only the first software control error type is reported in TC_SSRx.SWETYP. The TC_SRx.SECE flag is set at the first error occurrence within a series. |
Bit 2 – WPCREN Write Protection Control Enable
| Value | Description |
|---|---|
| 0 | Disables the write protection on control register if WPKEY corresponds to 0x54494D (“TIM” in ASCII). |
| 1 | Enables the write protection on control register if WPKEY corresponds to 0x54494D (“TIM” in ASCII). |
Bit 1 – WPITEN Write Protection Interrupt Enable
| Value | Description |
|---|---|
| 0 | Disables the write protection on interrupt registers if WPKEY corresponds to 0x54494D (“TIM” in ASCII). |
| 1 | Enables the write protection on interrupt registers if WPKEY corresponds to 0x54494D (“TIM” in ASCII). |
Bit 0 – WPEN Write Protection Enable
The Timer Counter clock of the first channel must be enabled to access this register.
See Register Write Protection for a list of registers that can be write-protected and Timer Counter clock conditions.
| Value | Description |
|---|---|
| 0 | Disables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII). |
| 1 | Enables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII). |