67.7.21 TC QDEC Interrupt Mask Register
| Name: | TC_QIMR |
| Offset: | 0xD0 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FMP | FIDX | FPHB | FPHA | MPE | QERR | DIRCHG | IDX | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – FMP Filtered Missing Pulse
| Value | Description |
|---|---|
| 0 | The interrupt on auto-corrected missing pulse is disabled. |
| 1 | The interrupt on auto-corrected missing pulse is enabled. |
Bit 6 – FIDX Filtered Index Line
| Value | Description |
|---|---|
| 0 | The interrupt on index line filtered contamination is disabled. |
| 1 | The interrupt on index line filtered contamination is enabled. |
Bit 5 – FPHB Filtered Phase B Line
| Value | Description |
|---|---|
| 0 | The interrupt on phase B line filtered contamination is disabled. |
| 1 | The interrupt on phase B line filtered contamination is enabled. |
Bit 4 – FPHA Filtered Phase A Line
| Value | Description |
|---|---|
| 0 | The interrupt on phase A line filtered contamination is disabled. |
| 1 | The interrupt on phase A line filtered contamination is enabled. |
Bit 3 – MPE Consecutive Missing Pulse Error
| Value | Description |
|---|---|
| 0 | The interrupt on the maximum number of consecutive missing pulses specified in MAXCMP is disabled. |
| 1 | The interrupt on the maximum number of consecutive missing pulses specified in MAXCMP is enabled. |
Bit 2 – QERR Quadrature Error
| Value | Description |
|---|---|
| 0 | The interrupt on quadrature error is disabled. |
| 1 | The interrupt on quadrature error is enabled. |
Bit 1 – DIRCHG Direction Change
| Value | Description |
|---|---|
| 0 | The interrupt on rotation direction change is disabled. |
| 1 | The interrupt on rotation direction change is enabled. |
Bit 0 – IDX Index
| Value | Description |
|---|---|
| 0 | The interrupt on IDX input is disabled. |
| 1 | The interrupt on IDX input is enabled. |