67.7.14 TC Extended Mode Register
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
| Name: | TC_EMRx |
| Offset: | 0x30 + x*0x40 [x=0..2] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NODIVCLK | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRIGSRCB[1:0] | TRIGSRCA[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 8 – NODIVCLK No Divided Clock
| Value | Description |
|---|---|
| 0 | The selected clock is defined by field TCCLKS in TC_CMRx. |
| 1 | The selected clock is peripheral clock and TCCLKS field (TC_CMRx) has no effect. |
Bits 5:4 – TRIGSRCB[1:0] Trigger Source for Input B
| Value | Name | Description |
|---|---|---|
| 0 | EXTERNAL_TIOBx | The trigger/capture input B is driven by external pin TIOBx |
| 1 | PWMx | For all channels: The trigger/capture input B is driven internally by the comparator output (see Synchronization with PWM) of the PWMx. |
Bits 1:0 – TRIGSRCA[1:0] Trigger Source for Input A
| Value | Name | Description |
|---|---|---|
| 0 | EXTERNAL_TIOAx |
The trigger/capture input A is driven by external pin TIOAx |
| 1 | PWMx |
For TC0, TC1.TIOB0, TC1.TIOB2: The trigger/capture input A is driven internally by PWMx. For TC1.TIOB1: The trigger/capture input A is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). |