67.7.1 TC Channel Control Register
This register can only be written if the WPCREN bit is cleared in the TC Write Protection Mode Register.
| Name: | TC_CCRx |
| Offset: | 0x00 + x*0x40 [x=0..2] |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWTRG | CLKDIS | CLKEN | |||||||
| Access | W | W | W | ||||||
| Reset | – | – | – |
Bit 2 – SWTRG Software Trigger Command
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | A software trigger is performed: the counter is reset and the clock is started. |
Bit 1 – CLKDIS Counter Clock Disable Command
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the clock. |
Bit 0 – CLKEN Counter Clock Enable Command
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the clock if CLKDIS is not 1. |