67.7.1 TC Channel Control Register

This register can only be written if the WPCREN bit is cleared in the TC Write Protection Mode Register.

Name: TC_CCRx
Offset: 0x00 + x*0x40 [x=0..2]
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      SWTRGCLKDISCLKEN 
Access WWW 
Reset  

Bit 2 – SWTRG Software Trigger Command

ValueDescription
0 No effect.
1 A software trigger is performed: the counter is reset and the clock is started.

Bit 1 – CLKDIS Counter Clock Disable Command

ValueDescription
0 No effect.
1 Disables the clock.

Bit 0 – CLKEN Counter Clock Enable Command

ValueDescription
0 No effect.
1 Enables the clock if CLKDIS is not 1.