67.7.16 TC Safety Status Register

Name: TC_SSRx
Offset: 0x38 + x*0x40 [x=0..2]
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 ECLASS   SWETYP[3:0] 
Access RRRRR 
Reset 00000 
Bit 2322212019181716 
 WPVSRC[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 WPVSRC[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
     SWESEQECGDWPVS 
Access RRRR 
Reset 0000 

Bit 31 – ECLASS Software Error Class

ValueNameDescription
0 WARNING

An abnormal access that does not have any impact.

1 ERROR

An abnormal access that may have an impact.

Bits 27:24 – SWETYP[3:0] Software Error Type (cleared on read)

ValueNameDescription
0 READ_WO

TC Channel x is enabled and a write-only register has been read (Warning).

1 WRITE_RO

TC Channel x is enabled and a write access has been performed on a read-only register (Warning).

2 UNDEF_RW

Access to an undefined address of the TC (Warning).

3 W_RARB_CAPT

TC_RAx or TC_RBx are written while channel is enabled and configured in capture mode (Error).

Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source (cleared on read)

When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.

Bit 3 – SWE Software Control Error (cleared on read)

ValueDescription
0

No software error has occurred since the last read of TC_SSRx.

1

A software error has occurred since the last read of TC_SSRx. The field SWETYP details the type of software error encountered.

Bit 2 – SEQE Internal Sequencer Error (cleared on read)

ValueDescription
0

No internal counter error has occurred since the last read of TC_SSRx. In normal operating conditions, SEQE is cleared.

1

An internal counter error has occurred since the last read of TC_SSRx. This flag can be set only under abnormal operating conditions resulting in clock glitch, etc. The detection is enabled if TC_CSRx.CLKSTA=1, TC_CMRx.WAVE=1, TC_CMRx.CPCTRG=1 and flag is set if TC_CVx > TC_RCx.

Bit 1 – CGD Clock Glitch Detected (cleared on read)

ValueDescription
0

The clock monitoring has not been corrupted since the last read of TC_SSRx.

1

The clock monitoring has been corrupted since the last read of TC_SSRx. This flag can be set under abnormal operating conditions.

Bit 0 – WPVS Write Protection Violation Status (cleared on read)

ValueDescription
0

No write protection violation has occurred since the last read of TC_SSRx.

1

A write protection violation has occurred since the last read of TC_SSRx. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.