47.6.6 FIFO Organization

The receiver embeds one 32-element FIFO, each element having a 32-bit width. The Receiver Holding register (SPDIFRX_RHR) is the output of the FIFO. Each time a sample is written in the FIFO, the flag SPDIFRX_ISR.RXRDY is set to ‘1’.

The data organization in the FIFO depends on the configuration of SPDIFRX_MR.PACK and SPDIFRX_MR.DATAWIDTH.

If SPDIFRX_MR.PACK=0, each FIFO element comprises one data sample and additional information (see Data Size Configuration Effect).

If SPDIFRX_MR.PACK=1, there is no additional information associated with each data sample, and the data are packed to optimize system memory amount required for processing. Thus the FIFO organization depends on the value written in the field SPDIFRX_MR.DATAWIDTH. See the figure below.

In 24-bit packed mode, the alignment is always maintained even if an overrun occurs.

When the FIFO is full, SPDIFRX_ISR.RXFULL is set to ‘1’ and an interrupt may be triggered. If an overrun occurs, SPDIFRX_ISR.OVERRUN is set to ‘1’ and an interrupt may also be triggered.