47.6.7 Channel Status Bit

The channel 1 status bits are stored in the Channel 1 Channel Status register (SPDIFRX_CH1SRx[x=0..5]), a 192-bit register that can be read directly from the user interface. Channel 2 status bits are stored in the Channel 2 Channel Status register (SPDIFRX_CH2SRx[x=0..5]). All 192 bits are valid when the block end status flag rises (SPDIFRX_ISR.BLOCKEND).

SPDIFRX_ISR.C1SC is set to ‘1’ if the channel status bits 0 to 31 differ from two consecutive blocks in channel 1.

SPDIFRX_ISR.C2SC is set to ‘1’ if the channel status bits 0 to 31 differ from two consecutive blocks in channel 2.