47.6.3 Clock and Data Recovery

When the SPDIFRX is first enabled by writing a ‘1’ in the bit RXEN in the Mode register (SPDIFRX_MR), the bit ULOCK in the Receiver Status register (SPDIFRX_RSR) is set, indicating that the synchronization of the receiver circuitry with the received stream is in progress. The SPDIFRX_RSR.ULOCK=1 if no synchronization is possible.

If there is no signal (no detection of falling/rising edges) on the SPDIF_RX line, the bit SPDIFRX_RSR.NOSIGNAL=‘1’.

If the SPDIF_RX line carries an SPDIF signal having a sampling frequency which does not meet the criteria defined in Data Rate, the bit SPDIFRX_RSR.LOWF= ‘1’.

If a non-SPDIF format is received/detected, the bit SPDIFRX_RSR.BADF= ‘1’. A non-SPDIF format is detected when the width of the larger pulse (located in preamble area) is not higher than 2.5 times the width of the minimum pulse or is greater than 4 times the width of the minimum pulse.

As soon as a valid SPDIF format is detected, the clock recovery circuitry is locked and the bi-mark data is decoded and the circuitry searches for predefined preamble values.

Once one of the preamble values is found, SPDIFRX_RSR.ULOCK is cleared and the bit LOCKED in the Interrupt Status register (SPDIFRX_ISR) is set to ‘1’. An interrupt can be triggered if LOCKED in the Interrupt Enable register (SPDIFRX_IER) is written to ‘1’.

The SPDIF_RX line is filtered by a digital filter to reduce noise before clock recovery. Any pulse with width lower than or equal to one GCLK clock period is eliminated.

The maximum lock time is 1.5 sample periods (1.5 frames). As soon as SPDIFRX_RSR.ULOCK is cleared, the payload data is stored in the FIFO and the channel 1 and 2 status bits and user data bits are stored. At the end of each block (192 frames), the bit SPDIFRX_ISR.BLOCKEND is set to ‘1’. If the SPDIFRX_ISR.BLOCKEND=1, the content of channel status (SPDIFRX_CH1SRx[x=0..5], SPDIFRX_CH2SRx[x=0..5]) and user data (SPDIFRX_CH1UDRx[x=0..5], SPDIFRX_CH2UDRx[x=0..5]) registers is valid.

When locked, in case of a loss of signal (32 consecutive 0’s or 1’s), the flag SPDIFRX_ISR.LOSS is set to ‘1’ and the recovery circuitry searches again for a synchronization pattern. When unlocked (SPDIFRX_RSR.ULOCK=1) the bit SPDIFRX_RSR.NOSIGNAL is set to ‘1’.

The data rate is monitored on-the-fly and any change is reported in the flag SPDIFRX_ISR.FSE.

If the data rate change does not create an important loss of synchronization, the clock recovery logic is reloaded with the new values (see Sample Frequency Measurement), thus providing a fast data recovery time. Anyway, in this case, a preamble error or a parity error can be detected.

A major data rate change can incur the loss of the clock recovery circuitry, resulting in preamble errors. It 16 consecutive preamble errors are detected, the clock recovery circuitry is automatically restarted, the flag SPDIFRX_ISR.FSE is set to “1” and as soon as circuitry is synchronized again, SPDIFRX_ISR.LOCK=’1’.

The potential causes of unlocked circuitry are provided in SPDIFRX_RSR when SPDIFRX_RSR.ULOCK is set to ‘1’. If there is no signal (no pulse detectable on the SPDIF RX line), SPDIFRX_RSR.NOSIGNAL is set to ‘1’. If the SPDIF_RX line carries a signal but the format cannot be analyzed as an SPDIFRX format, SPDIFRX_RSR.BADF is set to ‘1’. If the SPDIFRX format is correct but the GCLK frequency provided to the SPDIFRX module does not meet the minimum frequency conditions for the sample rate frequency carried on the SPDIF_RX line, SPDIFRX_RSR.LOWF is set to ‘1’.