8.4.7.3 Access Denials


ID_TZAESB_S Security Bit Setting in TZPM	ID_TZAESB_NS Security Bit Setting in TZPM	R/W Access to Secure Region from Non-Secure World	Bufferable Access (using MMU)	Data Abort	MATRIX Interrupt	TZC-400 Interrupt
Secure	Non-secure	Read	–	Yes / No	Yes	Yes
		Write	No	Yes / No	Yes	Yes
		Write	Yes	Yes / No	Yes⁽²⁾ / No	Yes
Secure	Secure	Read	–	Yes	Yes	No⁽¹⁾
		Write	No	Yes	Yes	No⁽¹⁾
		Write	Yes	Yes	Yes⁽²⁾	No⁽¹⁾
Non-secure	Non-secure	Read	–	Yes / No	Yes	Yes
		Write	No	Yes / No	Yes	Yes
		Write	Yes	Yes / No	Yes⁽²⁾ / No	Yes

Note:

Access denied by TZAESB, not propagated to TZC-400.
In the case of write burst accesses, MATRIX_MEARx registers might not return the address corresponding to the offending access: due to the AXI protocol, the TZC-400 response error indicates the last accessed address (not which of the consecutive accesses failed during the burst).