64.6.10.5 Instruction Frame

In order to control serial Flash memories, the QSPI can send instructions via the SPI bus (READ, PROGRAM, ERASE, LOCK, etc.). The QSPI includes a complete Instruction Frame register (QSPI_IFR) to ensure compatibility with all serial Flash memories.

An instruction frame includes:

• (Optional) An instruction code (see Continuous Read Mode).
• An address (size: 8, 16, 24 or 32 bits). The address is optional but is required by instructions such as READ, PROGRAM, ERASE, LOCK. By default, the address is 8 bits long, but can be increased up to 32 bits to support serial Flash memories larger than 128 Mbits.
• An option code (size: 1/2/4/8 bits). The option code can be used to activate some memory features.
• Dummy cycles. Dummy are required by some instructions.
• Data bytes. Data bytes are present for data transfer instructions such as READ or PROGRAM.

The instruction code, the address/option and the data can be sent with the Single-bit SPI, Dual SPI, Quad SPI or Octal SPI protocol.