64.6.10.14 HyperFlash Mode

The QSPI supports HyperFlash memories. To enable HyperFlash mode, set QSPI_IFR.PROTTYP to 3.

HyperFlash memories use Octal DDR communication. Recommendations provided in Octal DDR Mode must be followed.

In HyperFlash memories, the address field is merged with the instruction field, so QSPI_IFR.ADDREN must be set to 0 in this mode even if the address is used. No instruction code is required, therefore QSPI_WICR and QSPI_RICR are not used in this mode.

Once HyperFlash mode is enabled, the procedure to access the memory is the same as for classic QSPI memories. See Instruction Frame Transmission.

For the HyperFlash Write Buffer procedure, QSPI_IFR.HFWBEN must be set. When this bit is set, a new command will be issued for each halfword written. In this mode, halfword accesses are mandatory. See Figure 64-18 and Figure 64-19.

Note: In HyperFlash mode, some bits of the HyperFlash command are set automatically. For instance, the “Burst Type” bit of the HyperFlash command (bit 45) is always set to 1 (linear burst).