74.6.6.3.1 FLEXCOM TWI Timings

Table 74-32. TWI Interface Host Mode Timing Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
t_{LOW_TWCK}	TWCK low time	–	See notes ^{(1), (3), (4)}	–	µs
t_{HIGH_TWCK}	TWCK high time	–	See notes ^{(2), (3), (4)}	–	µs
f_TWCK	TWCK frequency	Standard Fast Fast-Mode Plus High-speed Mode	0	0.1 0.4 1 3.4 ⁽⁵⁾	MHz
t_HD(STA)	Hold time (repeated) START condition	Standard Fast Fast-Mode Plus	t_{HIGH_TWCK}	–	ns
t_HD(STA)	Hold time (repeated) START condition	High-speed Mode	FLEX_TWI_CWGR.BRSRCCLK = 1: t_{LOW_TWCK}⁽⁶⁾ FLEX_TWI_CWGR.BRSRCCLK = 0: 2 x t_{HIGH_TWCK}	–	ns
t_SU(STA)	Setup time for a repeated START condition	Standard Fast Fast-Mode Plus	t_{LOW_TWCK}	–	ns
t_SU(STA)	Setup time for a repeated START condition	High-speed Mode	FLEX_TWI_CWGR.BRSRCCLK = 1: t_{LOW_TWCK} FLEX_TWI_CWGR.BRSRCCLK = 0: 2 x t_{LOW_TWCK} ⁽⁶⁾	–	ns
t_HD(DAT)	Data hold time	Standard Fast Fast-Mode Plus	2 x t_MCK1	(HOLD + 3) × t_MCK1	ns
t_HD(DAT)	Data hold time	High-speed Mode	0	150 @ f_TWCK max = 1.7 MHz 70 @ f_TWCK max = 3.4 MHz	ns
t_SU(DAT)	Data setup time	Standard Fast Fast-Mode Plus	t_LOW – (HOLD + 3) × t_MCK1	–	ns
t_SU(DAT)	Data setup time	High-speed Mode	t_{LOW_TWCK}	–	ns
t_SU(STO)	Setup time for STOP condition	Standard Fast Fast-Mode Plus	FLEX_TWI_CWGR.BRSRCCLK = 1: t_{LOW_TWCK} FLEX_TWI_CWGR.BRSRCCLK = 0: t_{HIGH_TWCK}	–	ns
t_SU(STO)	Setup time for STOP condition	High-speed Mode	FLEX_TWI_CWGR.BRSRCCLK = 1: t_HIGH+1 FLEX_TWI_CWGR.BRSRCCLK = 0: t_{HIGH_TWCK}	–	ns
t_BUF	Bus free time between a STOP and a START condition	Standard Fast Fast-Mode Plus	t_{LOW_TWCK}	–	ns

Note:

TWCK low time (t_{LOW_TWCK}) ≥ t_LOWmin - t1*t_au → HSCLDIV/CLDIV = ( (t_{LOW_TWCK}/ t_PERIPH)-3) / 2^{CKDIV
or HSCKDIV} )
TWCK high time (t_{HIGH_TWCK)} ≥ t_HIGHmin + (t3-t2)*t_au → HSCHDIV/CHDIV = ( (t_{HIGH_TWCK} / t_PERIPH)-3) / 2^{CKDIV or
HSCKDIV} )
t_TWCK = (t_{LOW_TWCK} + t1*t_au) + t_r(max + (t_{HIGH_TWCK}+ (t3-t2)*t_au) + t_f(max)
The TWCK low/high time formulae in notes 1 and 2 are for Bit Rate Source Clock (BRSRCCLK) = 0 for all modes and RX Digital Filter (FILT) = 0 for Standard, Fast and FM+ Modes only. See FLEX_TWI_CWGR, FLEX_TWI_HSCWGR and FLEX_TWI_FILTR registers for more details.
1.7 MHz (Cbus 400 pF max), 3.4 MHz (Cbus 100 pF max). Timings in the above table involving t_{LOW_TWCK} and/or t_{HIGH_TWCK} may limit the TWCK maximum frequency when interfacing with an I2C client requiring strict I2C timings.
If computing HSCLDIV and/or HSCHDIV results in 0, t_SU(STA) and/or t_HD(STA) is equal to 6x t_{LOW_TWCK} and/or 6xt_{HIGH_TWCK}, respectively.

Table 74-33. Two-Wire Interface Client High-Speed Mode Timing Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
f_TWCK	TWCK clock frequency	–	–	3.4	MHz
t_HD(DAT)	Data hold time	f_TWCK = 1.7 MHZ	0	70	ns
t_HD(DAT)	Data hold time	f_TWCK = 3.4 MHz	0	150	ns
t_SU(DAT)	Data setup time	f_TWCK = 1.7 MHZ f_TWCK = 3.4 MHz	10	–	ns