9.3.1 System Reset

The dsPIC33AK128MC106 family of devices can generate an Internal System Reset (SYSRST) from multiple Reset sources, such as POR, BOR, MCLR, Watchdog Time-out Reset, SWR and CM.

A system Reset is active at the first POR and asserted until device configuration settings are loaded and the oscillator clock sources become stable. The system Reset is then deasserted, allowing the CPU to start fetching code after eight system clock cycles (SYSCLK).

BOR, MCLR and WDTO Resets are asynchronous events, and to avoid SFR and RAM corruptions, the system Reset is synchronized with the system clock. All other Reset events are synchronous.