9.3.3 Master Clear Reset (MCLR)

Whenever the master clear pin (MCLR) is driven low, the Reset event is synchronized with the System Clock (SYSCLK) before asserting the System Reset (SYSRST), provided the input pulse on MCLR is longer than a certain minimum width, as specified in the “Electrical Characteristics” chapter.

The MCLR pin provides a filter to minimize the effects of noise and to avoid unwanted Reset events. The Status bit, EXTR (RCON[7]), is set to indicate the MCLR Reset.