27.3.4.4 Number of Clock Cycles to Shift Data

The data from FIFO goes to the shift buffer. It takes two peripheral clock cycles to start moving the data words from FIFO to the shift buffer. The data from the shift buffer is then shifted to the CRC shift engine. It takes (DWIDTH[4:0] + 1) clock cycles to completely move the data from the shift buffer to the CRC shift engine. For example, if DWIDTH[4:0] = 5, then the data length is six bits (DWIDTH[4:0] + 1) and six cycles are required to shift the data. In this case, only six bits of a byte are shifted out. The two MSbs of each byte are don’t care bits. Similarly, for a 12-bit polynomial selection, the Most Significant four bits of each word are ignored.