27.3.4.3 FIFO to CRC Shift Engine

To start moving the data from the FIFO to the CRC shift buffer, the CRCGO bit (CRCCON[4]) must be set. The serial shifter starts shifting data from the shift buffer to the CRC shift engine, starting from the MSb first for LENDIAN = 0 and LSb first for LENDIAN = 1, when CRCGO = 1 and the value of VWORD[4:0] is greater than zero. If the CRCFUL bit was set earlier, then it is cleared when the VWORDx bits decrement by one. The VWORD[4:0] bits decrement by one when a FIFO location is moved to the shift buffer. The serial shifter continues shifting until the VWORD[4:0] bits reach zero; at this point, the CRCEMPTY bit becomes set to indicate that the FIFO is empty. If the CRCGO bit is cleared during a CRC calculation, then the CRC shift engine will stop calculating until the CRCGO bit is set.

The application can write into the FIFO while the shift operation is in progress. The CRCFULL bit should be monitored. If the CRCFULL bit is not set, another word can be written into the FIFO. At least one instruction cycle must pass after a write to the CRCDAT registers before a read of the valid value of the VWORD[4:0] bits.

When the VWORD[4:0] bits reach the maximum value for the configured value of the DWIDTH[4:0] bits, the CRCFULL bit becomes set. When the VWORD[4:0] bits reach zero, the CRCEMPTY bit becomes set. The FIFO is emptied and the VWORD[4:0] bits are set to ‘00000’ whenever the ON bit is ‘0’.