25.1 Device-Specific Information

Table 25-1. CLC Summary Table
CLC Module InstancesInputs per InstanceCLC OutputsPeripheral Bus Speed
484Slow
Table 25-2. DS1 Data Selection MUX 1 Signal Selection bits
Value (binary)Description
111SCCP4 auxiliary output
110SCCP2 auxiliary output
101CLKGEN13
100REFO1 clock output
011INTRC/LPRC clock source
010CLC3 out
001Slow peripheral clock (system clock/4)
000CLCINA I/O pin
Table 25-3. DS2 Data Selection MUX 2 Signal Selection bits
Value (binary)Description
111SCCP2 OCMP output
110SCCP1 OCMP output
101SCCP2 trigger output
100SCCP1 trigger output
011UART1 TX output
010Comparator 1 output
001CLC2 output
000CLCINB I/O pin
Table 25-4. DS3 Data Selection MUX 3 Signal Selection bits
Value (binary)Description
111SCCP4 OCMP output
110SCCP3 OCMP output
101CLC4 out
100UART1 RX input
011SPI1 Output (SDOx)
010Comparator 2 output
001CLC1 output
000CLCINC I/O pin
Table 25-5. DS4 Data Selection MUX 4 Signal Selection bits
Value (binary)Description
111SCCP3 auxiliary out
110SCCP1 auxiliary out
101CLCIND I/O pin
100Reserved
011SPI1 Input (SDIx)(1)
010Comparator 3 output
001CLC2 output
000PWM Event A
Note:
  1. Valid only when SPI output is remapped to a PPS pin.
  2. Whenever BFRC/256 (LPRC) is selected as the source for CLC, the LPRC clock should be enabled using the OSCCTRL.LPRCEN[4:0] register to get the LPRC clock output.