25.3 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x3A60	CLC1CON	31:24
		23:16					G4POL	G3POL	G2POL	G1POL
		15:8	ON				INTP	INTN
		7:0	LCOE	LCOUT	LCPOL			MODE[2:0]
0x3A64	CLC1SEL	31:24
		23:16
		15:8		DS4[2:0]				DS3[2:0]
		7:0		DS2[2:0]				DS1[2:0]
0x3A68	CLC1GLS	31:24	G4D4T	G4D4N	G4D3T	G4D3N	G4D2T	G4D2N	G4D1T	G4D1N
		23:16	G3D4T	G3D4N	G3D3T	G3D3N	G3D2T	G3D2N	G3D1T	G3D1N
		15:8	G2D4T	G2D4N	G2D3T	G2D3N	G2D2T	G2D2N	G2D1T	G2D1N
		7:0	G1D4T	G1D4N	G1D3T	G1D3N	G1D2T	G1D2N	G1D1T	G1D1N
0x3A6C ... 0x3A6F	Reserved
0x3A70	CLC2CON	31:24
		23:16					G4POL	G3POL	G2POL	G1POL
		15:8	ON				INTP	INTN
		7:0	LCOE	LCOUT	LCPOL			MODE[2:0]
0x3A74	CLC2SEL	31:24
		23:16
		15:8		DS4[2:0]				DS3[2:0]
		7:0		DS2[2:0]				DS1[2:0]
0x3A78	CLC2GLS	31:24	G4D4T	G4D4N	G4D3T	G4D3N	G4D2T	G4D2N	G4D1T	G4D1N
		23:16	G3D4T	G3D4N	G3D3T	G3D3N	G3D2T	G3D2N	G3D1T	G3D1N
		15:8	G2D4T	G2D4N	G2D3T	G2D3N	G2D2T	G2D2N	G2D1T	G2D1N
		7:0	G1D4T	G1D4N	G1D3T	G1D3N	G1D2T	G1D2N	G1D1T	G1D1N
0x3A7C ... 0x3A7F	Reserved
0x3A80	CLC3CON	31:24
		23:16					G4POL	G3POL	G2POL	G1POL
		15:8	ON				INTP	INTN
		7:0	LCOE	LCOUT	LCPOL			MODE[2:0]
0x3A84	CLC3SEL	31:24
		23:16
		15:8		DS4[2:0]				DS3[2:0]
		7:0		DS2[2:0]				DS1[2:0]
0x3A88	CLC3GLS	31:24	G4D4T	G4D4N	G4D3T	G4D3N	G4D2T	G4D2N	G4D1T	G4D1N
		23:16	G3D4T	G3D4N	G3D3T	G3D3N	G3D2T	G3D2N	G3D1T	G3D1N
		15:8	G2D4T	G2D4N	G2D3T	G2D3N	G2D2T	G2D2N	G2D1T	G2D1N
		7:0	G1D4T	G1D4N	G1D3T	G1D3N	G1D2T	G1D2N	G1D1T	G1D1N
0x3A8C ... 0x3A8F	Reserved
0x3A90	CLC4CON	31:24
		23:16					G4POL	G3POL	G2POL	G1POL
		15:8	ON				INTP	INTN
		7:0	LCOE	LCOUT	LCPOL			MODE[2:0]
0x3A94	CLC4SEL	31:24
		23:16
		15:8		DS4[2:0]				DS3[2:0]
		7:0		DS2[2:0]				DS1[2:0]
0x3A98	CLC4GLS	31:24	G4D4T	G4D4N	G4D3T	G4D3N	G4D2T	G4D2N	G4D1T	G4D1N
		23:16	G3D4T	G3D4N	G3D3T	G3D3N	G3D2T	G3D2N	G3D1T	G3D1N
		15:8	G2D4T	G2D4N	G2D3T	G2D3N	G2D2T	G2D2N	G2D1T	G2D1N
		7:0	G1D4T	G1D4N	G1D3T	G1D3N	G1D2T	G1D2N	G1D1T	G1D1N