10.2.1 System Traps and Interrupts

• CPU
  • Address error exception
  • Stack error exception
  • Math error trap due to arithmetic divide by zero
  • Math error trap due to arithmetic Accumulator A Overflow
  • Math error trap due to arithmetic Accumulator B Overflow
  • Math error trap due to arithmetic Accumulator A Catastrophic Overflow
  • Math error trap due to arithmetic Accumulator B Catastrophic Overflow
  • Math error trap due to arithmetic attempted out of range SFTAC
  • Program memory bus error
  • X-space read or write bus error
  • Y-space read or write bus error
  • Illegal instruction trap

• NVM Controller
  • NVM ECC single error correction interrupt
  • Erase programming complete/error interrupt CRC done

• DMA
  • DMA bus error trap
  • DMA channel interrupts

• ICD
  • ICD bus error

• DMT
  • DMT event generic trap

• WDT
  • WDT Sleep/Idle interrupt
  • WDT Run event generic trap

• PBU Cache
  • Cache parity error interrupt

• XRAM Controller
  • XRAM - ECC single-error correction interrupt
  • XRAM - PWB DED generic trap

• YRAM Controller
  • YRAM - ECC single-error correction interrupt
  • YRAM - PWB DED generic trap

The interrupt controller is responsible for pre-processing the peripheral interrupts and processor exceptions prior to them being presented to the processor core. The interrupts and traps are enabled, prioritized and controlled using centralized special function registers.