10.7.1 CPU Priority

An interrupt or a trap source must have a priority level greater than the current CPU priority to initiate an exception process. The CPU priority level is defined by a 4-bit value, SR.IPL [3:0]. The IPL [3] bit can be read at any time and may be cleared by software to allow trap handlers to jump to another process without having to execute a RETFIE.

IPL3: MSb of CPU Priority Level Nibble

1 = CPU Priority ≥ 8 (trap exception underway)

0 = CPU Priority < 8 (no trap exception underway)

IPL [2:0]: CPU Interrupt Priority Level status bits

111 = All interrupts disabled

110 = Level 7 interrupts enabled

101 = Level 6 and 7 interrupts enabled

100 = Level 5 through 7 interrupts enabled

011 = Level 4 through 7 interrupts enabled

010 = Level 3 through 7 interrupts enabled

001 = Level 2 through 7 interrupts enabled

000 = Level 1 through 7 interrupts enabled

The SR.IPL[2:0] status bits are readable and writable, so the user application can modify these bits to disable all sources of interrupts below a given priority level. For example, if IPL = 011, the CPU would not be interrupted by any source with a programmed priority level of one, two or three. All user interrupt sources can be disabled by setting SR.IPL[2:0] = 111.

Trap events have a higher priority than any user interrupt source. The IPL3 bit will be set by hardware when a trap occurs. This bit can be cleared, but not set by the user application. In some applications, the IPL3 bit will need to be cleared when a trap has occurred, and it will need to be branched to an instruction other than the instruction immediately after the one that originally caused the trap to occur.

The CPU interrupt priority is automatically modified during exception processing. However, provided interrupt nesting is enabled (INTCON1.NSTDIS= 0), IPL [2:0] are read/write bits and may also be manipulated by the user to dynamically modify the CPU interrupt priority. If interrupt nesting is disabled (INTCON1.NSTDIS = 1), IPL [2:0] shall by default be set to 0x7 and become read-only bits to prevent the user from inadvertently dropping the CPU interrupt priority (and causing any pending interrupts to nest).