20.5.1.2 Setting Baud Rate When Operating as a Bus Host

When operating as an I²C host, the module must generate the system SCLx clock. Generally, the I²C system clocks are specified to be either 100 kHz, 400 kHz or 1 MHz. The system clock rate is specified as the minimum SCLx low time (I2CxLBRG), plus the minimum SCLx high time (I2CxHBRG). In most cases, that is defined by two BRG periods (T_BRG).

The reload value for the BRG is the I2CxHBRG/I2CxLBRG register, as illustrated in Figure 20-5. When the BRG is loaded with this value, the generator counts down to zero and stops until another reload has taken place. The BRG is reloaded automatically on baud rate Restart. For example, if clock synchronization is taking place, the BRG will be reloaded when the SCLx pin is sampled high.

Note: The I2CxHBRG/I2CxLBRG register values that are less than four are not supported.

Figure 20-5. Baud Rate Generator Block Diagram

Equation 20-1 shows the formula for computing the BRG reload value.

Equation 20-1. BRG Reload Value Calculation

Where:

Typical value of delay is 200 ns.

Note: Equation 20-1 is only for a design guideline. Due to system-dependent parameters, the actual baud rate may differ slightly. Testing is required to confirm that the actual baud rate meets the system requirements; otherwise, the value of the I2CxHBRG/I2CxLBRG register has to be adjusted.

Table 20-19. I²C Clock Rates
F_PB	FSCL	I2CxLBRG/I2CxHBRG (Decimal)
200 MHz	1 MHz	57
200 MHz	400 kHz	207
200 MHz	100 kHz	957
100 MHz	1 MHz	27
100 MHz	400 kHz	102
100 MHz	100 kHz	477
50 MHz	1 MHz	12
50 MHz	400 kHz	50
50 MHz	100 kHz	237
16 MHz	1 MHz	—
16 MHz	400 kHz	13
16 MHz	100 kHz	73
8 MHz	1 MHz	—
8 MHz	400 kHz	5
8 MHz	100 kHz	35