4.2.4 Bus Matrix

The Bus Matrix (BMX) arbitrates memory accesses in the event that two independent initiators are trying to access the same target. Initiators are a set of modules that can initiate a read or write transaction to another module called a target. The BMX connects the initiator to the target and determines which initiator gets priority (based on a fixed priority scheme and the SFR priority). The type of access, program or data, is determined by the initiator bus. It supports concurrent accesses by different initiators as long as they have an independent target. For example, CPU to SFR could be concurrent with DMA to RAM.

BMX Initiators include:

Initiator 0 – CPU X Data Bus (CPU XDS)
Initiator 1 – CPU Y Data Bus (CPU YDS)
Initiator 2 – DMA
Initiator 3 – CPU Instruction Bus (CPU IS)
Initiator 4 – Nonvolatile Memory Controller
Initiator 5 – In-Circuit Debugger

BMX Targets include:

Program Flash (Data reads)
Peripheral Buses (through Bus Splitter)
XRAM and YRAM interfaces
Debug RAM

Note: XRAM and YRAM simultaneous access is supported.

Figure 4-2 shows the typical block diagram of the Bus Matrix.

Figure 4-2. Bus Matrix Block Diagram with Initiators and Targets

Note: See Table 4-14 for initiator/target options.