4.4.5.1 Valid Targets

Not all targets are valid destinations for each initiator. Refer to Table 4-14 for details on which targets are valid for each initiator.

Accessing an invalid target will generate a bus error and set the BADTGTWERR (BMXxERR[16]) or BADTGTRERR (BMXxERR[0] bit.

Table 4-14. Valid Targets by Initiator
InitiatorsTargets
PS ReadXRAMYRAMDebug RAMSFRs
CPU X Data✔✔✔If Debug mode is enabled✔
CPU Y Data—✔✔If Debug mode is enabled—
DMA✔✔✔—✔
CPU Instruction—✔✔——
NVM✔————
ICD—✔✔✔✔