10.3.2 Collapsed Interrupt Vector

The IVT can be collapsed by configuring the IVTC bit within the IVTCREG register. While trap handlers remain unaffected by this setting, all peripheral interrupts are directed to a singular location that follows trap vectors. When the IVTC bit is set to 1, all peripheral interrupts utilize a common vector, which is located at the offset address 0x24.

The collapsed peripheral interrupt vector is placed in the reserved interrupt location. The trap interrupts are not collapsed and the peripheral interrupts are pointed to one location, which is placed after the trap’s interrupt location, as shown in Figure 10-2.

The potential application of RIVT and CIVT is in scenarios where the processor is operating within a secure or boot memory segment and encounters a trap or an interrupt. In such cases, the secure boot software is required to assign the interrupt base address to a designated interrupt vector address located within the secure or boot memory segment. Upon completion of its operations, the secure boot software will then assign predetermined values to specific memory segments. Additionally, the secure boot software has the option to set the Interrupt Vector Table Collapse (IVTC) to "1", thereby consolidating the interrupt vector for all peripherals into a single entry. Once the secure boot software has finalized its processes, it may reset this bit, effectively deactivating the collapsed IVT feature.