10.13.1 Interrupt Latency

Interrupt Latency: CPU Highest Priority Bus Main:

If the CPU is set to be the highest priority RAM bus Main (BMX register BMXINITPR[31:0] = 32’b0), the CPU will offer a variable latency response for all exceptions solely based upon the execution time of the instructions underway (that are completed) at the time of the exception. The interrupt latency from the time when the system clock samples the pending interrupts to the time the first instruction of the ISR has been fetched will be:

max. latency = t_arb + ρ + ɳ + Δ cycles

min. latency = t_arb + 1 + ɳ + Δ cycles

Where:

t_arb Arbitration time (cycles)

ρ = Total instruction execution time during exception processing (cycles)

ɳ = Vector memory access time (cycles)

Δ = Program memory access time (cycles)

The above relationship applies to exceptions occurring during any instruction, including during a PS access. The latency is expressed as a range for any given instruction because the interrupt may arrive at the beginning or end of an instruction.

Note: ρ = Total instruction execution time during exception processing depends on current instruction under execution, and may vary anywhere between 1-2 cycles depending upon the instruction.

η = Vector memory access time may vary anywhere between 4-7 cycles and

Δ = Program memory access time may vary between 1-7 cycles depending on the placement of the IVT and ISR or the current status of the Instruction cache. Refer to the PBU section for more details.

Interrupt Latency:CPU Not Highest Priority Main:

If the CPU is not the highest priority RAM bus Main, the CPU will offer a variable latency response for all exceptions that may also include additional delays resulting from higher priority bus master RAM access requests. That is, when the CPU is not operating as the highest priority bus Main, exception processing is no longer an atomic operation and may be stalled as necessary to provide bus access to another Main.