3.3.7.1 SR: CPU STATUS Register

The dsPIC33A CPU has a 32-bit STATUS Register (SR). A detailed description of the CPU SR is shown in SR.

SR contains:

• All ALU Operation Status flags
• The CPU Interrupt Priority Level Status bits, IPL[3:0]
• The REPEAT Loop Active Status bit, RA (SR[4])

• The DSP Adder/Subtracter Status bits

The SR bits are readable/writable with the following exceptions:

• The RA bit (SR[4]) is read-only.
• The OA, OB (SR[15:14]), OAB (SR[11]), SA, SB (SR[13:12]) and SAB (SR[10]) bits are readable and writable; however, once set, they remain set until cleared by the user application, regardless of the results from any subsequent DSP operations.
  Note: Clearing the SAB bit also clears both the SA and SB bits. Similarly, clearing the OAB bit also clears both the OA and OB bits. A description of the STATUS Register bits affected by each instruction is provided in the “dsPIC33A Programmer’s Reference Manual” .
• The CTX bit (SR[18:16]) is read-only; it reflects which W register context is currently in use by the CPU.
• The VF bit (SR[23]) is read-only.