6.3.4.1 CRC Control Register

The NVMCRCCON register manages several controls for CRC operations, including the CRCEN bit, START bit, CRCIDL field, and DELAY control field. These controls are used to configure and manage the CRC function.

Starting a CRC Operation: Set the CRCEN and START bits. The hardware clears the START bit when the CRC calculation is complete, and an interrupt request is generated.

Canceling a CRC Operation: Clear the CRCEN bit. This disables the CRC function, sets START to 0, and resets NVMCRCDATA to 0x0000_0000.

DELAY Field: This field allows CRC read accesses to be rate-limited. This feature is useful for run-time self-checking of flash to limit the performance impact of background CRC calculations on other firmware functions.

If DELAY=0x00, no rate limiting is applied, allowing continuous CRC reads.

If DELAY is non-zero, it inserts a specified delay (in system clock cycles) between CRC read accesses. Arbitration may cause the actual delay to be longer.

CRCIDL Field: Controls when the CRC function operates:

• CRC operates in Idle mode and stops when the CPU is running.
• CRC operates when the CPU is running and stops in Idle mode.
• CRC operates both when the CPU is running and in Idle mode.

CRCIDL provides control options suitable for both foreground and background flash self-check operations.