11.4.10.1 CN Configuration and Operation

The CN pins are configured as follows:

  1. Disable CPU interrupts.
  2. Set the desired CN I/O pin as an input by setting the corresponding TRISx register bits = 1.
    Note: If the I/O pin is shared with an analog peripheral, it may be necessary to configure this pin as digital input.
  3. Enable the CN Module by setting the ON bit (CNCONx[15]) = 1.
  4. Enable individual CN input pins; enable optional pull-ups or pull-downs.
  5. Read the corresponding PORTx registers to clear the CN interrupt.
  6. Configure the CNx Interrupt Priority bits, CNxIP[2:0].
  7. Clear the CNx Interrupt Flag bit by setting the CNxIF bit (IFSx register) = 0.
  8. Configure the CNx pin interrupt for either Mismatch mode or Edge Detect mode using the CNSTYLE bit (CNCONx[11]). If Mismatch mode is selected, enable the individual CNx function using the CNEN0x bits. If Edge Detect mode is selected, use the CNEN0x bits to enable positive edge detection and the CNEN1x bits to enable negative edge detection.
  9. Enable the CNx Interrupt Enable bit by setting the CNxIE bit (IECx register) = 1.
  10. Enable CPU interrupts.

    The CNSTATx/CNFx registers indicate whether a change occurred on the corresponding pin since the last read of the PORTx bit.

    The CNFx registers indicate a valid edge detect event has occurred when CNSTYLE = 1. CNFx bits need to be cleared by the user to set up the CN logic to detect the next edge transition. In Edge Detect mode, a CN interrupt can be controlled to occur only during a rising or falling edge condition on a pin. The CNSTATx are read-only registers that indicate a valid Mismatch mode event has occurred when CNSTYLE = 0.

    When a CN interrupt occurs in Mismatch mode, the user should read the PORTx register associated with the CN pins. This will clear the mismatch condition and set up the CN logic to detect the next pin change. The CN pins have a minimum input pulse-width specification. Refer to the “Electrical Characteristics” chapter to learn more.