55.3 Power Supply

Table 55-7. Power Supply Electrical Specifications
DC CHARACTERISTICSStandard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated)

Operating Temperature:

-40°C ≤ TA ≤ +85°C for Industrial Temperature

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
REG_1VDDCORE_CIN(1)VDDCORE Input Bypass parallel Capacitor pair 3.764.7—µFBulk Ceramic or solid Tantalum with ESR <0.5Ω.

Minimum and maximum represent absolute

values including cap tolerances

80100—nFCeramic XR7 with ESR <0.5Ω
REG_5VDD_CIN(1)VDD Input Bypass parallel Capacitor pair 810—µFBulk Ceramic or solid Tantalum with ESR <0.5Ω

Separate BULK capacitor for each VDD

80100—nFCeramic XR7 with ESR <0.5Ω on all VDD pins
REG_9VREFx_CIN(1)External VREFx Input Bypass parallel Capacitor pair 810—µFBulk Ceramic or solid Tantalum with ESR <0.5Ω
80100—nFCeramic XR7 with ESR <0.5Ω
REG_13VBAT_CIN (1)VBAT Input Bypass parallel Capacitor pair 810—µFBulk Ceramic or solid Tantalum with ESR <0.5Ω
80100—nFCeramic XR7 with ESR <0.5Ω
REG_17AVDD_CIN (1)AVDD Input Bypass parallel Capacitor pair 810—µFBulk Ceramic or solid Tantalum with ESR <0.5Ω
80100—nFCeramic XR7 with ESR <0.5Ω
REG_23AVDD_LEXT(2)AVDD series Ferrite Bead DCR (DC Resistance)——0.1Ω≥600Ω @ 100 MHz
REG_25Ferrite Bead current Rating500——mA —
REG_27VSW_LEXT(3,4,5)Buck Switch Mode Regulator Inductor Inductance

(If LDO Mode not used)

—10—µHShielded Inductor ONLY (If used in BUCK mode else No Connect)
REG_29Inductor DCR (DC Resistance)——0.36Ω—
REG_31Inductor ISAT Rating 500——mA—
REG_33BUCK_PEFFBuck Mode Power Efficiency—66—%IOUT = 100 uA
REG_35—74—%IOUT = 100 mA
REG_36VDDCOREVDDCORE Voltage Range—1.2—VCPU active, cache and prefetch

disabled, executing "while(1)" from Flash

REG_37VDDVDD Input Voltage Range1.713.33.63VBOD33 Disabled
REG_37AIDDVDD_MAXVDD/AVVD Max Current——130mAI/O pins configured as inputs
REG_39AVDD AVDD Input Voltage Range1.713.33.63VBOD33 Disabled
REG_41VBATVBAT Input Voltage Range1.71 —3.63VBOD33 Disabled
REG_41AIDDVBAT_MAXVBAT Max Current——315µAOSCULP32K, BOD and RTC enabled
REG_43SVDD_RVDD, AVDD, VDDIOB Rise Ramp Rate

to Ensure Internal Power-on Reset Signal

0.2—100mV/µsFailure to meet this specification may lead to start-up or unexpected behaviors
REG_44SVDD_FVDD, AVDD, VDDIOB Falling Ramp Rate

to Ensure Internal Power-on Reset Signal

 ——50mV/µsFailure to meet this specification may cause the device to not detect reset
REG_45VPORPower-on Reset 0.97—1.64VVDD Power up/Down (See Param REG_43, VDD Ramp Rate)
REG_47VBOD33 (6,7)VDD BOD (All modes)1.46—1.56V

SUPC.BOD33.LEVEL[7:0] = 0x00 (Min Value) ,

SUPC.BOD33.HYST[3:0] = 0x02

1.61—1.71

SUPC.BOD33.LEVEL[7:0] = 0x19 (Recommended Value) ,

SUPC.BOD33.HYST[3:0] = 0x02

1.63—1.73

SUPC.BOD33.LEVEL[7:0] = 0x1C (Recommended Value) ,

SUPC.BOD33.HYST[3:0] = 0x02

2.95—3.12

SUPC.BOD33.LEVEL[7:0] = 0xFF (Max Value) ,

SUPC.BOD33.HYST[3:0] = 0x00

REG_51VBOD33LEVEL_STEPVBOD33 step size (SUPC.BOD33.LEVEL)—6—mVStep Size
REG_52VBOD33HYST_STEPVBOD33 Hysteresis step size (SUPC.BOD33.HYST)—6—mVStep Size
REG_53TRSTExternal RESET valid active pulse width1——µsMinimum reset active time to guarantee CPU reset.
REG_54VDDIOB (8, 9,10)IOB Supply Voltage1.713.33.63VWith BOD33 disabled and BOD12 enabled.
Note:
  1. All bypass caps should be located immediately adjacent to pins and on the same side of the PCB as the MCU. Each primary power supply group VDD, AVDD, VDDCORE, and VBAT should have one bulk capacitor and on all power pins everywhere a 100 nF bypass cap.
  2. Ferrite Bead ISAT(min) ≥ (IDDANA(max) * 1.15).
  3. User must select either LDO or BUCK mode. The modes are mutually exclusive.
  4. Buck Inductor ISAT(min) ≥ ((ICAPACITOR + IVDDCORE_MAX) * 1.25) when BUCK mode enabled (shielded inductor only).
  5. Given:

    BUCK VSW output pin impedance = ~4 ohms

    Buck Inductor DCR = ~0.2 ohms (Check Inductor Manufacturing Specification)

    C= VDDCORE Bypass Capacitance

    RVSW = VSW output pin impedance + Buck Inductor DCR

    e = 2.71828

    Recommended Inductor ISAT margin 25%

    VDDCORE bypass bulk capacitor charging current through inductor:

    ICAPACITOR = (VDDCORE / RVSW) e-t/RC where t = 0 is worst case

    THEREFORE:

    Inductor ISAT(max) = ((ICAPACITOR + IVDDCORE_PEAK_SURGE) * 1.25) = (((VDDCORE / RVSW) e-t/RC + IVDDCORE_PEAK_SURGE) * 1.25)

    Example:
    • VDDCORE bypass capacitors = 4.7 µF + 100 nF
    • IVDDCORE_PEAK_SURGE = 120 mA
    Inductor ISAT(max) = (((VDDCORE / RVSW) e-t/RC + IVDDCORE_PEAK_SURGE) * 1.25)

    = (((1.2 / 4.2) * 2.71828-(0 / 4.3*4.8µF) + 120mA) * 1.25)

    = (((286 mA * 1) + 120 mA) * 1.25)

    = ((286 mA + 120 mA) * 1.25)

    = ~508 mA

  6. VBOD(min) = (1.5 + (SUPC.BOD33.LEVEL[7:0] * VBOD33LEVEL_STEP))

    VBOD(max) = (VBOD(min) + (SUPC.BOD33.HYST[3:0] * VBOD33HYST_STEP))

  7. If a hysteresis value is programmed, the following equation must be respected to avoid any overflow on VBOD(max) : LEVEL[7:0] value < 255 - HYST[3:0] value.
  8. The same voltage must be applied to VDD and VDDANA. VDDIOB must be lower or equal to VDD and VDDANA.
  9. When I/O pads in the VDDIOB cluster are multiplexed as analog pads, VDDANA is used to power the I/O. Using this configuration may result in an electrical conflict if the VDDIOB voltage is different from that of VDD and VDDANA. If the application has such requirements, it is required to power VDDIOB, VDD and VDDANA from the same supply source to ensure that they are always at the same voltage.
  10. VDDIOB pins are only available on the SG41 device.