55.26 I²S Electrical Specifications

Figure 55-5. I²S Host Mode Timing Diagram

Table 55-35. I²S Host Mode Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial Temperature
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
I2S_1	f_{M_MCK}	Host MCK Frequency	—	—	12.5	MHz	VDD = 1.8V or VDD(min.) whichever is greater, C_LOAD= 20 pF(max.)
I2S_1	f_{M_MCK}	Host MCK Frequency	—	—	12.5	MHz	VDD = 3.3V, C_LOAD= 20 pF(max.)
I2S_3	t_MCKL	MCK Output Low Time	1/(2*f_{M_MCK} )	—	—	ns	—
I2S_5	t_MCKH	MCK Output High Time	1/(2*f_{M_MCK} )	—	—	ns	—
I2S_7	t_MCKR	MCK Rise Time	DI_25			ns	DI_25: Refer to I/O Pin Electrical Specifications
I2S_9	t_MCKF	MCK Fall Time	DI_27			ns	DI_27: Refer to I/O Pin Electrical Specifications
I2S_11	f_{M_SCK}	Host SCK Frequency			10.29	MHz	VDD = 1.8V or VDD(min.) whichever is greater, C_LOAD= 20 pF(max.)
I2S_11	f_{M_SCK}	Host SCK Frequency	—	—	11.4	MHz	VDD = 3.3V, C_LOAD= 20 pF(max.)
I2S_13	t_SCKL	SCK Output Low Time	1/(2*f_{M_SCK})	—	—	ns	—
I2S_15	t_SCKH	SCK Output High Time	1/(2*f_{M_SCK})	—	—	ns	—
I2S_17	t_SCKR	SCK Rise Time	DI_25			ns	DI_25: Refer to I/O Pin Electrical Specifications
I2S_19	t_SCKF	SCK Fall Time	DI_27			ns	DI_27: Refer to I/O Pin Electrical Specifications
I2S_21	t_{M_FSVALID}	Host Frame Sync Valid	—	—	5.3	ns	VDD = 1.8V or VDD(min.) whichever is greater, C_LOAD= 20 pF(max.)
I2S_21	t_{M_FSVALID}	Host Frame Sync Valid	—	—	4.2	ns	VDD = 3.3V, C_LOAD = 20 pF(max)
I2S_23	t_{M_FSHOLD}	Host Frame Sync Hold	0	—	—	ns	VDD = 1.8V or VDD(min.) whichever is greater, C_LOAD= 20 pF(max.)
I2S_23	t_{M_FSHOLD}	Host Frame Sync Hold	0	—	—	ns	VDD = 3.3V, C_LOAD= 20 pF(max.)
I2S_25	t_{M_DISETUP}	Host Data Input Setup	16.4	—	—	ns	VDD = 1.8V or VDD(min.) whichever is greater, C_LOAD= 20 pF(max.)
I2S_25	t_{M_DISETUP}	Host Data Input Setup	11.9	—	—	ns	VDD = 3.3V, C_LOAD= 20 pF(max.)
I2S_27	t_{M_DIHOLD}	Host Data Input Hold	3.4	—	—	ns	VDD = 1.8V or VDD(min.) whichever is greater, C_LOAD= 20 pF(max.)
I2S_27	t_{M_DIHOLD}	Host Data Input Hold	3.4	—	—	ns	VDD = 3.3V, C_LOAD= 20 pF(max.)
I2S_29	t_{M_DOVALID}	Host Data Output Valid	—	—	3.7	ns	VDD = 1.8V or VDD(min.) whichever is greater, C_LOAD= 20 pF(max.)
I2S_29	t_{M_DOVALID}	Host Data Output Valid	—	—	3	ns	VDD = 3.3V, C_LOAD= 20 pF(max.)
I2S_31	t_{M_DOHOLD}	Host Data Output Hold	0	—	—	ns	VDD = 1.8V or VDD(min.) whichever is greater, C_LOAD= 20 pF(max.)
I2S_31	t_{M_DOHOLD}	Host Data Output Hold	0	—	—	ns	VDD = 3.3V, C_LOAD= 20 pF(max.)
I2S_33	f_{GCLK_I2S}	I²S Max GLK Input Clock Freq	—	—	FCLK_29	MHz	FCLK_29: Refer to Maximum Clock Frequencies Electrical Specifications

Figure 55-6. I²S Client Mode Timing Diagram

Table 55-36. I²S Client Mode Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial Temperature
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
I2S_41	f_{S_SCK}	SCK Client Frequency	—	—	15.48	MHz	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_41	f_{S_SCK}	SCK Client Frequency	—	—	15.83	MHz	VDD=3.3V, C_LOAD=20pF(MAX)
I2S_43	t_{S_FSVALID}	Frame Sync Valid	4.1	—	—	ns	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_43	t_{S_FSVALID}	Frame Sync Valid	3.8	—	—	ns	VDD=3.3V, C_LOAD=20pF(MAX)
I2S_45	t_{S_FSHOLD}	Frame Sync Hold	0	—	—	ns	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_45	t_{S_FSHOLD}	Frame Sync Hold	0	—	—	ns	VDD=3.3V, C_LOAD=20pF(MAX)
I2S_47	t_{S_DISSETUP}	Data Input Client Setup	2.8	—	—	ns	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_47	t_{S_DISSETUP}	Data Input Client Setup	2.1	—	—	ns	VDD=3.3V, C_LOAD=20pF(MAX)
I2S_49	t_{S_DISHOLD}	Data Input Client Hold	0	—	—	ns	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_49	t_{S_DISHOLD}	Data Input Client Hold	0	—	—	ns	VDD=3.3V, C_LOAD=20pF(MAX)
I2S_51	t_{S_DSOVALID}	Data Output Client Valid	—	—	16.9	ns	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_51	t_{S_DSOVALID}	Data Output Client Valid	—	—	12.3	ns	VDD=3.3V, C_LOAD=20pF(MAX)
I2S_53	t_{S_DSOHOLD}	Data Output Client Hold	5.3	—	—	ns	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_53	t_{S_DSOHOLD}	Data Output Client Hold	4.1	—	—	ns	VDD=3.3V, C_LOAD=20pF(MAX)

Figure 55-7. I²S PDM2 Mode Timing Diagram

Table 55-37. I²S PMD2 Mode Electrical Specifications
AC CHARACTERISTICS			Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial Temperature
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
I2S_55	t_SCK	SCK Frequency	—	—	41.9	MHz	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_55	t_SCK	SCK Frequency	—	—	44.5	MHz	VDD=3.3V, C_LOAD=20pF(MAX)
I2S_57	t_PDM2LS	PDM Left Channel Setup	16.4	—	—	ns	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_57	t_PDM2LS	PDM Left Channel Setup	11.9	—	—	ns	VDD=3.3V, C_LOAD=20pF(MAX)
I2S_59	t_PDM2LH	PDM Left Channel Hold	3.4	—	—	ns	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_59	t_PDM2LH	PDM Left Channel Hold	3.4	—	—	ns	VDD=3.3V, C_LOAD=20pF(MAX)
I2S_61	t_PDM2RS	PDM Right Channel Setup	15.6	—	—	ns	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_61	t_PDM2RS	PDM Right Channel Setup	11.8	—	—	ns	VDD=3.3V, C_LOAD=20pF(MAX)
I2S_63	t_PDM2RH	PDM Right Channel Hold	4.4	—	—	ns	VDD=1.8V or VDD(min) whichever is greater, C_LOAD=20pF(MAX)
I2S_63	t_PDM2RH	PDM Right Channel Hold	3.4	—	—	ns	VDD=3.3V, C_LOAD=20pF(MAX)

PIC32CX SG41/SG60/SG61 Family Data Sheet

55.26 I2S Electrical Specifications

55.26 I²S Electrical Specifications