18.7.11 DFLL48M Synchronization
| Name: | DFLLSYNC |
| Offset: | 0x2C |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DFLLMUL | DFLLVAL | DFLLCTRLB | ENABLE | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 4 – DFLLMUL DFLLMUL Synchronization Busy
This bit is cleared when the synchronization of DFLLMUL register between the clock domains is complete.
This bit is set when the synchronization of DFLLMUL register between clock domains is started.
The DFLLMUL synchronization only applies for write operations.
Bit 3 – DFLLVAL DFLLVAL Synchronization Busy
This bit is cleared when the synchronization of DFLLVAL register between the clock domains is complete.
This bit is set when the synchronization of DFLLVAL register between clock domains is started.
The DFLLVAL synchronization applies for read and write operations.
Bit 2 – DFLLCTRLB DFLLCTRLB Synchronization Busy
This bit is cleared when the synchronization of DFLLCTRLB register between the clock domains is complete.
This bit is set when the synchronization of DFLLCTRLB register between clock domains is started.
The DFLLCTRLB synchronization only applies for write operations.
Bit 1 – ENABLE ENABLE Synchronization Busy
This bit is cleared when the synchronization of ENABLE register bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE register bit between clock domains is started.