18.7.2 Interrupt Enable Clear
| Name: | INTENCLR |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DPLL1LDRTO | DPLL1LTO | DPLL1LCKF | DPLL1LCKR | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DPLL0LDRTO | DPLL0LTO | DPLL0LCKF | DPLL0LCKR | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFLLRCS | DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| XOSCFAIL1 | XOSCFAIL0 | XOSCRDY1 | XOSCRDY0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 27 – DPLL1LDRTO DPLL1 Loop Divider Ratio Update Complete Interrupt Enable
0: The DPLL1 Loop Divider Ratio Update Complete interrupt is disabled.
1: The DPLL1 Loop Divider Ratio Update Complete interrupt is enabled, and an interrupt request will be generated when the DPLL1 Loop Divider Ratio Update Complete Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DPLL1 Loop Divider Ratio Update Complete Interrupt Enable bit, which disables the DPLL1 Loop Divider Ratio Update Complete interrupt.
Bit 26 – DPLL1LTO DPLL1 Lock Timeout Interrupt Enable
0: The DPLL1 Lock Timeout interrupt is disabled.
1: The DPLL1 Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL1 Lock Timeout Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DPLL1 Lock Timeout Interrupt Enable bit, which disables the DPLL1 Lock Timeout interrupt.
Bit 25 – DPLL1LCKF DPLL1 Lock Fall Interrupt Enable
0: The DPLL1 Lock Fall interrupt is disabled.
1: The DPLL1 Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL1 Lock Fall Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DPLL1 Lock Fall Interrupt Enable bit, which disables the DPLL1 Lock Fall interrupt.
Bit 24 – DPLL1LCKR DPLL1 Lock Rise Interrupt Enable
0: The DPLL1 Lock Rise interrupt is disabled.
1: The DPLL1 Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL1 Lock Rise Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DPLL1 Lock Rise Interrupt Enable bit, which disables the DPLL1 Lock Rise interrupt.
Bit 19 – DPLL0LDRTO DPLL0 Loop Divider Ratio Update Complete Interrupt Enable
0: The DPLL0 Loop Divider Ratio Update Complete interrupt is disabled.
1: The DPLL0 Loop Divider Ratio Update Complete interrupt is enabled, and an interrupt request will be generated when the DPLL0 Loop Divider Ratio Update Complete Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DPLL0 Loop Divider Ratio Update Complete Interrupt Enable bit, which disables the DPLL0 Loop Divider Ratio Update Complete interrupt.
Bit 18 – DPLL0LTO DPLL0 Lock Timeout Interrupt Enable
0: The DPLL0 Lock Timeout interrupt is disabled.
1: The DPLL0 Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL0 Lock Timeout Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DPLL0 Lock Timeout Interrupt Enable bit, which disables the DPLL0 Lock Timeout interrupt.
Bit 17 – DPLL0LCKF DPLL0 Lock Fall Interrupt Enable
0: The DPLL0 Lock Fall interrupt is disabled.
1: The DPLL0 Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL0 Lock Fall Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DPLL0 Lock Fall Interrupt Enable bit, which disables the DPLL0 Lock Fall interrupt.
Bit 16 – DPLL0LCKR DPLL0 Lock Rise Interrupt Enable
0: The DPLL0 Lock Rise interrupt is disabled.
1: The DPLL0 Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL0 Lock Rise Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DPLL0 Lock Rise Interrupt Enable bit, which disables the DPLL0 Lock Rise interrupt.
Bit 12 – DFLLRCS DFLL Reference Clock Stopped Interrupt Enable
0: The DFLL Reference Clock Stopped interrupt is disabled.
1: The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated when the DFLL Reference Clock Stopped Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables the DFLL Reference Clock Stopped interrupt.
Bit 11 – DFLLLCKC DFLL Lock Coarse Interrupt Enable
0: The DFLL Lock Coarse interrupt is disabled.
1: The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Coarse Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DFLL Lock Coarse Interrupt Enable bit, which disables the DFLL Lock Coarse interrupt.
Bit 10 – DFLLLCKF DFLL Lock Fine Interrupt Enable
0: The DFLL Lock Fine interrupt is disabled.
1: The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Fine Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DFLL Lock Fine Interrupt Enable bit, which disables the DFLL Lock Fine interrupt.
Bit 9 – DFLLOOB DFLL Out Of Bounds Interrupt Enable
0: The DFLL Out Of Bounds interrupt is disabled.
1: The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the DFLL Out Of Bounds Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DFLL Out Of Bounds Interrupt Enable bit, which disables the DFLL Out Of Bounds interrupt.
Bit 8 – DFLLRDY DFLL Ready Interrupt Enable
0: The DFLL Ready interrupt is disabled.
1: The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the DFLL Ready Interrupt Enable bit, which disables the DFLL Ready interrupt.
Bits 2, 3 – XOSCFAIL XOSC n Clock Failure Interrupt Enable
0: The XOSC n Clock Failure interrupt is disabled.
1: The XOSC0 Clock Failure interrupt is enabled, and an interrupt request will be generated when the XOSC0 Clock Failure Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the XOSC n Clock Failure Interrupt Enable bit, which disables the XOSC n Clock Failure interrupt.
Bits 0, 1 – XOSCRDY XOSC n Ready Interrupt Enable
0: The XOSC n Ready interrupt is disabled.
1: The XOSC0 Ready interrupt is enabled, and an interrupt request will be generated when the XOSC n Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a '1' to this bit will clear the XOSC n Ready Interrupt Enable bit, which disables the XOSC n Ready interrupt.