18.7.15 DPLL Synchronization Busy
| Name: | DPLLSYNCBUSY |
| Offset: | 0x3C + n*0x14 [n=0..1] |
| Reset: | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DPLLRATIO | ENABLE | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 2 – DPLLRATIO DPLL Loop Divider Ratio Synchronization Status
0: The DPLLRATIO register has been synchronized.
1: The DPLLRATIO register value has changed and its synchronization is in progress.
Bit 1 – ENABLE DPLL Enable Synchronization Status
0: The DPLLnCTRLA.ENABLE bit has been synchronized.
1: The DPLLnCTRLA.ENABLE bit value has changed and its synchronization is in progress.