18.7.16 DPLL Status
| Name: | DPLLSTATUS |
| Offset: | 0x40 + n*0x14 [n=0..1] |
| Reset: | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKRDY | LOCK | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 1 – CLKRDY DPLL Clock Ready
0: The DPLLn output clock is off.
1: The DPLLn output clock in on.
Bit 0 – LOCK DPLL Lock Status
0: The DPLLn Lock signal is cleared, when the DPLLn is disabled or when the DPLLn is trying to reach the target frequency.
1: The DPLLn Lock signal is asserted when the desired frequency is reached.