18.7.14 DPLL Control B
| Name: | DPLLCTRLB |
| Offset: | 0x38 + n*0x14 [n=0..1] |
| Reset: | 0x00000020 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DIV[10:8] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DCOEN | DCOFILTER[2:0] | LBYPASS | LTIME[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| REFCLK[2:0] | WUF | FILTER[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
Bits 26:16 – DIV[10:0] Clock Divider
These bits are used to set the XOSC clock division factor and can be calculated with following formula:
Bit 15 – DCOEN DCO Filter Enable
0: Disable DCO filter controller. Sigma-Delta DAC is automatically set the PLL itself.
1: Enable DCO filter controller. DCOFILTER[2:0] is used to select sigma-delta DAC filter bandwidth.
Bits 14:12 – DCOFILTER[2:0] Sigma-Delta DCO Filter Selection
These bits select the DPLLn sigma-delta DCO filter type, as shown in the table below:
| DCOFILTER[2:0] | Capacitor (pF) | Bandwidth Fn (MHz) |
|---|---|---|
| 0x0 | 0.5 | 3.21 |
| 0x1 | 1 | 1.6 |
| 0x2 | 1.5 | 1.1 |
| 0x3 | 2 | 0.8 |
| 0x4 | 2.5 | 0.64 |
| 0x5 | 3 | 0.55 |
| 0x6 | 3.5 | 0.45 |
| 0x7 | 4 | 0.4 |
Bit 11 – LBYPASS Lock Bypass
Bits 10:8 – LTIME[2:0] Lock Time
Write these bits to select the lock time-out value, as shown in the figure below:
| Value | Name | Description |
|---|---|---|
| 0x0 | Default | No time-out. Automatic lock. |
| 0x1 | Reserved | |
| 0x2 | Reserved | |
| 0x3 | Reserved | |
| 0x4 | 800US | Time-out if no lock within 800 us |
| 0x5 | 900US | Time-out if no lock within 900 us |
| 0x6 | 1MS | Time-out if no lock within 1 ms |
| 0x7 | 1P1MS | Time-out if no lock within 1.1 ms |
Bits 7:5 – REFCLK[2:0] Reference Clock Selection
Write these bits to select the DPLLn clock reference, as shown in the table below:
| Value | Name | Description |
|---|---|---|
| 0x0 | GCLK | Dedicated GCLK clock reference |
| 0x1 | XOSC32 | XOSC32K clock reference (default) |
| 0x2 | XOSC0 | XOSC0 clock reference |
| 0x3 | XOSC1 | XOSC1 clock reference |
| Other | - | Reserved |
Bit 4 – WUF Wake Up Fast
0: DPLLn clock is output after startup and lock time.
1: DPLLn clock is output after startup time.
Bits 3:0 – FILTER[3:0] Proportional Integral Filter Selection
These bits select the DPLLn digital filter type, as shown in the table below:
| FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor |
|---|---|---|
| 0x0 | 92.7 kHz | 0.76 |
| 0x1 | 131 kHz | 1.08 |
| 0x2 | 46.4 kHz | 0.38 |
| 0x3 | 65.6 kHz | 0.54 |
| 0x4 | 131 kHz | 0.56 |
| 0x5 | 185 kHz | 0.79 |
| 0x6 | 65.6 kHz | 0.28 |
| 0x7 | 92.7 kHz | 0.39 |
| 0x8 | 46.4 kHz | 1.49 |
| 0x9 | 65.6 kHz | 2.11 |
| 0xA | 23.2 kHz | 0.75 |
| 0xB | 32.8 kHz | 1.06 |
| 0xC | 65.6 kHz | 1.07 |
| 0xD | 92.7 kHz | 1.51 |
| 0xE | 32.8 kHz | 0.53 |
| 0xF | 46.4 kHz | 0.75 |