12.6.5 Bridge Interrupt Flag Status
These flags are cleared by writing a '1' to the corresponding bit.
These flags are set when an access error is detected by the corresponding AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
| Name: | INTFLAGAHB |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| QSPI | SDHC1 | SDHC0 | PUKCC | HPB3 | HPB2 | HPB1 | |||
| Access | RW | RW | RW | RW | RW | RW | RW | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HPB0 | RAMDMACICM | RAMDMAWR | RAMPPPDSU | RAMCM4S | SEEPROM | FLASH_ALT | FLASH | ||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 14 – QSPI Interrupt Flag for QSPI
This flag is set when an access error is detected by the QSPI AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the QSPI interrupt flag.
Bit 13 – SDHC1 Interrupt Flag for SDHC1
This flag is set when an access error is detected by the SDHC1 AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the SDHC1 interrupt flag.
Bit 12 – SDHC0 Interrupt Flag for SDHC0
This flag is set when an access error is detected by the SDHC0 AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the SDHC0 interrupt flag.
Bit 11 – PUKCC Interrupt Flag for PUKCC
This flag is set when an access error is detected by the PUKCC AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the PUKCC interrupt flag.
Bit 10 – HPB3 Interrupt Flag for AHB-APB Bridge D
This flag is set when an access error is detected by the AHB-APB Bridge D Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the HPB3 interrupt flag.
Bit 9 – HPB2 Interrupt Flag for AHB-APB Bridge C
This flag is set when an access error is detected by the AHB-APB Bridge C Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the HPB2 interrupt flag.
Bit 8 – HPB1 Interrupt Flag for AHB-APB Bridge B
This flag is set when an access error is detected by the AHB-APB Bridge B Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the HPB1 interrupt flag.
Bit 7 – HPB0 Interrupt Flag for AHB-APB Bridge A
This flag is set when an access error is detected by the AHB-APB Bridge A Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the HPB0 interrupt flag.
Bit 6 – RAMDMACICM Interrupt Flag for RAMDMACICM
This flag is set when an access error is detected by the RAMDMACICM AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the RAMDMACICM interrupt flag.
Bit 5 – RAMDMAWR Interrupt Flag for RAMDMAWR
This flag is set when an access error is detected by the RAMDMAWR AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the RAMDMAWR interrupt flag.
Bit 4 – RAMPPPDSU Interrupt Flag for RAMPPPDSU:
This flag is set when an access error is detected by the RAMPPPDSU AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the RAMPPPDSU interrupt flag.
Bit 3 – RAMCM4S Interrupt Flag for RAMCM4S
This flag is set when an access error is detected by the RAMCM4S AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the RAMCM4S interrupt flag.
Bit 2 – SEEPROM Interrupt Flag for SEEPROM
This flag is set when an access error is detected by the SEEPROM AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the SEEPROM interrupt flag.
Bit 1 – FLASH_ALT Interrupt Flag for FLASH_ALT
This flag is set when an access error is detected by the FLASH_ALT AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the FLASH_ALT interrupt flag.
Bit 0 – FLASH Interrupt Flag for FLASH
This flag is set when an access error is detected by the FLASH AHB Client, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' has no effect.
Writing a '1' to this bit will clear the FLASH interrupt flag.