42.7.8 Status

Note: This register is read- and write-synchronized: SYNCBUSY.STATUS must be checked to ensure the STATUS register synchronization is complete.
Name: STATUS
Offset: 0x0C
Reset: 0x0040
Property: Read-Synchronized, Write-Synchronized

Bit 15141312111098 
   CCBUFV1CCBUFV0  FILTERBUFVPRESCBUFV 
Access RRRR 
Reset 0000 
Bit 76543210 
 DIRSTOPHERRWINERR MPERRIDXERRQERR 
Access RRRWRWRWRWRW 
Reset 0100000 

Bits 12, 13 – CCBUFV Compare Channel x Buffer Valid

The bit is set when a new value is written to the corresponding CCBUF register.

The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE condition.

Bit 9 – FILTERBUFV Filter Buffer Valid

This bit is set when a new value is written to the PRESCALERBUF register.

The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE condition.

This bit is always read '0' when COUNTER operation mode is selected.

Bit 8 – PRESCBUFV Prescaler Buffer Valid

This bit is set when a new value is written to the PRESC register.

The bit is cleared by writing a '1' to the corresponding location or automatically cleared on an UPDATE condition.

Bit 7 – DIR Direction Status Flag

This bit reflects the HALL/QDEC direction.

in COUNTER mode, this bits is always read '0'.

Note: STATUS.DIR bit status is not relevant if a direction change occurs (INTFLAG.DIR=1).
ValueDescription
0 Clockwise direction.
1 Counter-clockwise direction.

Bit 6 – STOP Stop

This bit reflects the HALL/QDEC decoding status.

In COUNTER mode, this bits is always read '0'.

ValueDescription
0 PDEC/HALL decoding is running.
1 PDEC/HALL decoding is stopped.

Bit 5 – HERR Hall Error Flag

This flag is set when an invalid HALL code is detected.

The flag is cleared by writing a '1' to this bit location.

Outside of HALL mode, this bits is always read '0'.

Bit 4 – WINERR Window Error Flag

This flag is set when the counter is outside the window monitor.

The flag is cleared by writing a '1' to this bit location.

Outside of HALL mode, this bits is always read '0'.

Note:
  1. Disable the WINERR (INTCLR.WINERR = 1) at first error detection, then re-enable it once the error root cause at the application level is solved.
  2. Ignore the Windows Error (WINERR) flag after a START command execution, or when leaving standby.

Bit 2 – MPERR Missing Pulse Error flag

This flag is set when a missing pulse error condition is detected.

The flag is cleared by writing a '1' to this bit location.

Outside of QDEC mode, this bits is always read '0'.

Bit 1 – IDXERR Index Error Flag

This flag is set when an index error condition is detected.

The flag is cleared by writing a '1' to this bit location.

Outside of QDEC mode, this bits is always read '0'.

Bit 0 – QERR Quadrature Error Flag

This flag is set when an invalid QDEC transition is detected.

The flag is cleared by writing a '1' to this bit location.

Outside of QDEC mode, this bits is always read '0'.