42.7.1 Control A
Name: | CTRLA |
Offset: | 0x00 |
Reset: | 0x00000000 |
Property: | PAC Write-Protection, Enable-Protected |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
MAXCMP[3:0] | ANGULAR[2:0] | ||||||||
Access | RW | RW | RW | RW | RW | RW | RW | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
PINVEN2 | PINVEN1 | PINVEN0 | PINEN2 | PINEN1 | PINEN0 | ||||
Access | RW | RW | RW | RW | RW | RW | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
PEREN | SWAP | ALOCK | CONF[2:0] | ||||||
Access | RW | RW | RW | RW | RW | RW | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
RUNSTDBY | MODE[1:0] | ENABLE | SWRST | ||||||
Access | RW | RW | RW | RW | W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bits 31:28 – MAXCMP[3:0] Maximum Consecutive Missing Pulses
These bits define the threshold for the maximum consecutive missing pulses in AUTOC configuration of the QDEC mode.
Outside of AUTOC configuration of QDEC mode, these bits have no effect.
These bits are not synchronized.
Bits 26:24 – ANGULAR[2:0] Angular Counter Length
In QDEC mode, these bits define the size of the Angular counter within COUNT. Angular counter size is equal to CTRLA.ANGULAR+9. The remaining MSB of the COUNTER register are used for counting revolutions.
For example, CTRLA.ANGULAR=0 defines the 9 LSB of COUNT as Angular counter and the residual 7 MSB of COUNT as Revolution counter. CTRLA.ANGULAR=7 will define a 16-bit Angular counter and no Revolution counter.
Outside of QDEC mode, these bits have no effect.These bits are not synchronized.
ANGULAR[2:0] | Angular counter | Revolution counter |
---|---|---|
0x0 | COUNTER[0:8] | COUNTER[9:15] |
0x1 | COUNTER[0:9] | COUNTER[10:15] |
0x2 | COUNTER[0:10] | COUNTER[11:15] |
0x3 | COUNTER[0:11] | COUNTER[12:15] |
0x4 | COUNTER[0:12] | COUNTER[13:15] |
0x5 | COUNTER[0:13] | COUNTER[14:15] |
0x6 | COUNTER[0:14] | COUNTER[15] |
0x7 | COUNTER[0:15] | no revolution counter |
Bits 20, 21, 22 – PINVENx I/O Pin x Invert Enable
When this bit is written to '1', the corresponding input pin active level is inverted. This bit has no effect if the PINENx bit is zero.
In COUNTER mode only PINVEN[0] is significant.
This bit is not synchronized.
Value | Description |
---|---|
0 | Pin active level is not inverted. |
1 | Pin active level is inverted. |
Bits 16, 17, 18 – PINENx PDEC Input From Pin x Enable
This bit enables the I/O pin x as signal input.
In COUNTER mode, only PINVEN[0] is significant.
This bit is not synchronized.
Value | Description |
---|---|
0 | Event line is the signal input. |
1 | I/O pin is the signal input. |
Bit 15 – PEREN Period Enable
This bit is used to enable the CC0 register as counter period.
This bit is not synchronized.
Value | Description |
---|---|
0 | Period register function is disabled. |
1 | CC0 is acting as counter period register. |
Bit 14 – SWAP PDEC Phase A and B Swap
This bit is used to swap input source of signal 0 and 1.
In COUNTER mode this bit has no effect.
This bit is not synchronized.
Value | Description |
---|---|
0 | The input sources of signal 0 and 1 are not swapped. |
1 | The input sources of signal 0 and 1 are swapped. |
Bit 11 – ALOCK Auto Lock
When this bit is set, the Lock Update bit in Control B register (CTRLB.LUPD) is set by hardware when an UPDATE condition is detected.
This bit is not synchronized.
Value | Description |
---|---|
0 | Auto Lock is disabled. |
1 | Auto Lock is enabled. |
Bits 10:8 – CONF[2:0] PDEC Configuration
These bits define the PDEC configuration.
Outside of QDEC mode, these bits have no effect.
These bits are not synchronized.
Value | Name | Description |
---|---|---|
0 | X4 | Quadrature decoder direction |
1 | X4S | Secure Quadrature decoder direction |
2 | X2 | Decoder direction |
3 | X2S | Secure decoder direction |
4 | AUTOC | Auto correction mode |
Bit 6 – RUNSTDBY Run in Standby
This bit is used to keep the PDEC running in standby mode.
This bit is not synchronized.
Value | Description |
---|---|
0 | The PDEC is halted in standby. |
1 | The PDEC continues to run in standby. |
Bits 3:2 – MODE[1:0] Operation Mode
These bits select one of the QDEC, HALL, COUNTER modes.
These bits are not synchronized.
Value | Name | Description |
---|---|---|
0x0 | QDEC | QDEC operating mode |
0x1 | HALL | HALL operating mode |
0x2 | COUNTER | COUNTER operating mode |
Bit 1 – ENABLE Enable
Due to synchronization, there is delay between writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately, and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value | Description |
---|---|
0 | The peripheral is disabled. |
1 | The peripheral is enabled. |
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the PDEC (except DBGCTRL) to their initial state, and the PDEC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST willl be cleared when the Reset is complete.
- When the CTRLA.SWRST is written, the user must poll the SYNCBUSY.SWRST bit to know when the reset operation is complete.
- During a SWRST, access to registers/bits without the SWRST are disallowed until the SYNCBUSY.SWRST is cleared by hardware.
Value | Description |
---|---|
0 | There is no Reset operation ongoing. |
1 | A Reset operation is ongoing. |