27.5.6.2 NVM Write

The entire NVM main address space except the BOOTPROT section can be erased by a debugger Chip Erase command. Alternatively, blocks or pages can be individually erased using the Erase Page (EP) or Erase Block (EB) depending on the targeted address space. The NVM can be programmed using the Write Page (WP) or Write Quad Word (WQW) commands depending on the targeted address space. AHB writes automatically update the ADDR register. ADDR is write locked by the NVMCTRL until the pagebuffer write completes or until the appropriate write command has been passed to the command interface when in automatic write mode. Write commands are not supported in all address spaces, see the table below. These commands are detailed further in this section.

Issuing an unsupported command on an address space sets the PROGE interrupt flag.

After programming the NVM main array, the region that the page resides in can be locked to prevent spurious write or erase sequences. Locking is performed on a per-region basis, and so locking a region locks all pages inside the region.

Data to be written to the NVM block is written through AHB and stored in an internal buffer called the page buffer. If the NVMCTRL is busy processing a write command (STATUS.READY=0) then the AHB bus is stalled upon an AHB write until the ongoing command completes. Writing the page buffer is allowed during a block erase operation. The page buffer contains the same number of bytes as an NVM page. Writes to the page buffer must be 32 bits. 16-bit or 8-bit writes to the page buffer is not allowed, and will cause a PAC error. Internally, writes to the page buffer are on a 64-bit basis through the page buffer load data registers (PBLDATA[1] and PBLDATA[0]). The PBLDATA register is a holding register for writes to the same 64-bit page buffer section. Data within a 64-bit section can be written in any order. Crossing a 64- bit boundary will reset the PBLDATA register to all ones. The following example assumes startup from reset where the current address is 0 and PBLDATA is all ones. Only 64 bits of the page buffer are written at a time, but 128 bits are shown for reference.

Sequential 32-bit write example:

• 32-bit 0x1 written to address 0
  • Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, PBLDATA[63:32], 0x00000001}
  • PBLDATA[63:0] = {PBLDATA[63:32], 0x00000001}
• 32-bit 0x2 written to address 1
  • Page buffer[127:0] = {0xFFFFFFFF_FFFFFFFF, 0x00000002, PBLDATA[31:0]}
  • PBLDATA[63:0] = {0x00000002, PBLDATA[31:0]}
• 32-bit 0x3 written to address 2 (crosses 64-bit boundary)
  • Page buffer[127:0] = 0xFFFFFFFF_00000003_00000002_00000001
  • PBLDATA[63:0] = 0xFFFFFFFF_00000003

Random access writes to 32-bit words within the page buffer will overwrite the opposite word within the same 64-bit section with ones. In the following example, 0x00000001 is overwritten with 0xFFFFFFFF from the third write due to the 64-bit boundary crossing. Only 64 bits of the page buffer are written at a time, but 128 bits are shown for reference.

Random access 32-bit AHB write example:

• 32-bit 0x1 written to address 2
  • Page buffer[127:0] = 0xFFFFFFFF_00000001_FFFFFFFF_FFFFFFFF
  • PBLDATA[63:0] = 0xFFFFFFFF_00000001
• 32-bit 0x2 written to address 1
  • Page buffer[127:0] = 0xFFFFFFFF_00000001_00000002_FFFFFFFF
  • PBLDATA[63:0] = 0x00000002_FFFFFFFF
• 32-bit 0x3 written to address 3
  • Page buffer[127:0] = 0x00000003_FFFFFFFF_00000002_FFFFFFFF
  • PBLDATA[63:0] = 0x00000003_0xFFFFFFFF

BANKA and BANKB share the same page buffer. Writing to the NVM block via the AHB bus is buffered in the page buffer. For each AHB bus write, the address is stored in the ADDR register. After the page buffer has been loaded with the required number of bytes, the page can be written to the addressed location by setting CMD to Write Page to write the NVM main array and setting the key value to CMDEX. The LOAD bit in the STATUS register indicates whether the page buffer has been loaded or not. Before writing the page to memory, the accessed block must be erased.

Several write modes are supported and configured through CTRLA.WMODE:

• Manual (MAN):

This is the default configuration. Because the address is automatically stored in ADDR during AHB write operations, the last given address will be present in the ADDR register. There is no need to load the ADDR register manually, unless a different page in memory is to be written. A write should be issued before writing to a different page.

• Automatic Write With Double Word Granularity (ADW):

Automatically writes data with double-word granularity. In this case the WQW command is triggered at the quad-word addressed by ADDR when the last word in a double-word aligned block is written. The other double-word inside the page buffer must be all one. STATUS.READY goes low during the NVM write operation. INTFLAG.DONE flag is set upon completion.

• Automatic Write With Quad Word Granularity (AQW):

Automatically writes data with quad-word granularity. In this case the WQW command is triggered at the quad-word addressed by ADDR when the last word in a quad-word aligned block is written. STATUS.READY goes low during the NVM write operation. INTFLAG.DONE flag is set upon completion.

• Automatic Write With Page Granularity (AP):

Automatically writes data with page granularity. In this case the WP command is triggered at the page addressed by ADDR when the last word in a page aligned block is written. STATUS.READY goes low during the NVM write operation. INTFLAG.DONE flag is set upon completion.

These write modes are supported for writes in the main address space and in the USER page. The USER page doesn’t support write page, if the AP mode is selected writes in the USER page will be done in AQW mode. This avoids to change WMODE by software while mixing writes in the main address space and in the USER page.

Procedure for Manual Page Writes (WMODE=MAN)

The block to be written must be erased before the write command is given.

• Write to the page buffer by addressing the NVM main address space directly
• Write the page buffer to memory:
  • CMD=WP (and CMDEX) to write the full content of the page buffer into the NVM at the page pointed by ADDR
  • CMD=WQW (and CMDEX) to write into the NVM the page buffer quad word pointed by ADDR
• The READY bit in the STATUS register will be low while programming is in progress, and access through the AHB in the same bank will be stalled.

Procedure for Automatic Writes (WMODE=ADW or AQW or APW)

The block to be written must be erased before the last write to the page buffer is performed. The internal write operation will begin when the second word is written for WMODE = ADW, when the fourth word is written for WMODE = AQW, and when the last word of the page is written for WMODE = APW.

Note that partially written pages must be written with a manual write.

If the command interface is already processing a command, the AHB is stalled until the automatic write command is taken. Therefore it is possible to chain write commands without polling STATUS.READY. For applications that must not stall the AHB bus the automatic write must be used carefully: STATUS.READY must be checked after each double-word or quad-word or page buffer write depending on WMODE before chaining with a new write to avoid stalling the bus.

• Write to the page buffer by addressing the NVM main address space directly.
  • When the word location in the page buffer is written, the double word or quad word or page is automatically written to NVM main address space.
• STATUS.READY will be zero while programming is in progress and access through the AHB will be stalled.