6.1 Reset (NRST) Pin

The NRST pin is unidirectional. It is managed by the external host controller and can be driven low to provide a Reset signal to reset the PL460. It resets the core and the peripherals. There is no constraint on the length of the Reset pulse.

It is recommended to connect the NRST pin to a GPIO of the host controller whose reset state is configured as pull-down. If the GPIO reset configuration is high-impedance, a pull-down resistor connected to GND must be used to ensure the timing of the power-on sequence. If using a GPIO with pull-up as reset configuration, then a 100 nF capacitor connected to GND must be used to ensure the timing of the power-on sequence.

When using the Sleep mode functionality, the NRST and STBY signals must be connected to a GPIO in the host controller with an internal pull-down default reset configuration to avoid enabling Sleep mode until the host boots.

To enter Sleep mode, it is required to reset the device (driving the NRST pin low) before enabling the STBY input. To exit Sleep mode, the STBY pin must be disabled before releasing NRST.

Refer to 11.8 Power On Considerations to view the timing constraints using this pin.