4.9.14 External Interrupts

The external interrupts are triggered by the INT0 or INT1 pin or any of the PCINT[13:0] pins. Note that, if enabled, the interrupts trigger even if the INT0, INT1 or PCINT[13:0] pins are configured as outputs. This feature makes it possible to generate a software interrupt. The pin change interrupt PCI0 triggers if any enabled PCINT[7:0] (PORTB) pin toggles. The pin change interrupt PCI1 triggers if any enabled PCINT[13:8] (PORTC) pin toggles. The PCMSK1 and PCMSK0 registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT[13:0] are detected asynchronously. The user can use these interrupts for waking the part from sleep modes other than IDLEMode.

The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a LOW level. This is set up as indicated in the specification for the external interrupt control register A (EICRA). If INT0 or INT1 interrupts are enabled and are configured as level triggered, an interrupt triggers as long as the pin is held at the trigger level.

Note: The recognition of falling or rising edge interrupt on INT0 or INT1 requires the presence of an I/O clock. See System Clock and Clock Options from Related Links.

The level interrupts on INT0 or INT1 are detected asynchronously. The user can use these interrupts for waking up the part from sleep modes other than IDLEMode. The I/O clock is stopped in all sleep modes except IDLEMode.

If debouncing is enabled, the pin change interrupts or external interrupts for these pins are only triggered if the debounce condition is fulfilled. See I/O Ports from Related Links.

Note: If a level-triggered interrupt is used for wake-up from Power-down mode, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the start-up time, the MCU still wakes up, but no interrupt is generated.