The following figure presents the principal clock systems in the AVR and their distribution. Not
all of the clocks need to be active at a given time. To reduce power consumption, stop
the clocks to modules that are not in use by using different sleep modes. See Sleep
Modes and Active Power Reduction from Related Links. Fine-grained clock gating
can be performed by using the power reduction registers (PRR0, PRR1 and PRR2).
Additional power reduction bits are available for the RX DSP. See RDPR in the
RX DSP Control Register Description from Related Links.Figure 4-41. AVR Clock Systems
The AVR clock management supports the switching of the AVR clock source during operation. This allows for a start-up with the fast RC oscillator (CLKFRC), then switching to the more accurate XTO-based clock (CLKXTO4, CLKXTO6) used as the system clock (CLKSYS).
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