4.9.13 Specific Interrupts Handling
This section describes the specifics of interrupt handling. For a general explanation of AVR interrupt handling, see Reset and Interrupt Handling from Related Links.
After a reset, the interrupt vector table base address is always located at address 0x0000 in the ROM. The base address can be configured for the ATA8210 with the IVSEL bit in MCUCR.
The reset vector is independent of the interrupt vector table base address and can be configured for the ATA8210 with the BOOTRST fuse. See Fuse Low Byte from Related Links.
Vector No. | Program Address | Source | Interrupt Definition |
|---|---|---|---|
1 | 0x000 | RESET | External Pin, Power-On/Brown-Out Reset, Watchdog Reset |
2 | 0x002 | INT0 | External Interrupt Request 0 |
3 | 0x004 | INT1 | External Interrupt Request 1 |
4 | 0x006 | PCI0 | Pin Change Interrupt Request 0 |
5 | 0x008 | PCI1 | Pin Change Interrupt Request 1 |
6 | 0x00A | VMON | Voltage Monitoring Interrupt |
7 | 0x00C | AVCCR | AVCC Reset Interrupt |
8 | 0x00E | AVCCL | AVCC Low Interrupt |
9 | 0x010 | T0INT | Timer0 Interval Interrupt |
10 | 0x012 | T1COMP | Timer1 Compare Match Interrupt |
11 | 0x014 | T1OVF | Timer1 Overflow Interrupt |
12 | 0x016 | T2COMP | Timer2 Compare Match Interrupt |
13 | 0x018 | T2OVF | Timer2 Overflow Interrupt |
14 | 0x01A | T3CAP | Timer3 Capture Event Interrupt |
15 | 0x01C | T3COMP | Timer3 Compare Match Interrupt |
16 | 0x01E | T3OVF | Timer3 Overflow Interrupt |
17 | 0x020 | T4CAP | Timer4 Capture Event Interrupt |
18 | 0x022 | T4COMP | Timer4 Compare Match Interrupt |
19 | 0x024 | T4OVF | Timer4 Overflow Interrupt |
20 | 0x026 | T5COMP | Timer5 Compare Match Interrupt |
21 | 0x028 | T5OVF | Timer5 Overflow Interrupt |
22 | 0x02A | SPI | SPI Serial Transfer Complete Interrupt |
23 | 0x02C | SRX_FIFO | SPI RX Buffer Interrupt |
24 | 0x02E | STX_FIFO | SPI TX Buffer Interrupt |
25 | 0x030 | SSM | Sequencer State Machine Interrupt |
26 | 0x032 | DFFLR | Data FIFO fill level reached Interrupt |
27 | 0x034 | DFOUE | Data FIFO overflow or underflow error Interrupt |
28 | 0x036 | SFFLR | SFIFO fill level reached Interrupt |
29 | 0x038 | SFOUE | SFIFO FIFO overflow or underflow error Interrupt |
30 | 0x03A | TMTCF | Reserved |
31 | 0x03C | UHF_WCOB | UHF receiver wake-up ok on RX path B |
32 | 0x03E | UHF_WCOA | UHF receiver wake-up ok on RX path A |
33 | 0x040 | UHF_SOTB | UHF receiver start of telegram ok on RX path B |
34 | 0x042 | UHF_SOTA | UHF receiver start of telegram ok on RX path A |
35 | 0x044 | UHF_EOTB | UHF receiver end of telegram on RX path B |
36 | 0x046 | UHF_EOTA | UHF receiver end of telegram on RX path A |
37 | 0x048 | UHF_NBITB | UHF receiver new bit on RX path B |
38 | 0x04A | UHF_NBITA | UHF receiver new bit on RX path A |
39 | 0x04C | EXCM | External input Clock monitoring Interrupt |
40 | 0x04E | ERDY | EEPROM Ready Interrupt |
41 | 0x050 | SPMR (1) | Store Program Memory Ready |
42 | 0x052 | IDFULL | IDSCAN Full Interrupt |
- Only valid for the ATA8210.